From 09c7ba0f88939de7e4d4ccea87e28b4d65594dc0 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Oct 2018 15:16:07 +0100
Subject: [PATCH] redirect RS2 to sv_proc_t class

---
 riscv/insns/amomaxu_d.h   |  2 +-
 riscv/insns/amominu_d.h   |  2 +-
 riscv/sv_insn_redirect.cc |  6 +++++-
 riscv/sv_insn_redirect.h  | 14 +++++++++++++-
 4 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index 12b1733..e5ae07f 100644
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,3 +1,3 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); }));
+WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return (lhs > RS2) ? lhs : RS2; }));
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 15b6c0a..a03a1d6 100644
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,3 +1,3 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); }));
+WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return (lhs < RS2) ? lhs : RS2; }));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index e222922..616ed33 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -13,7 +13,11 @@ reg_t (sv_proc_t::READ_REG)(uint64_t i)
 }
 */
 
-RS1::operator reg_t () const {
+RS1::operator reg_t () const & {
     return _insn->p->get_state()->XPR[_insn->rs1()];
 }
 
+RS2::operator reg_t () const & {
+    return _insn->p->get_state()->XPR[_insn->rs2()];
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 2e71c95..2efcce3 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -6,6 +6,7 @@
 #include "sv_decode.h"
 
 #undef RS1
+#undef RS2
 
 class processor_t;
 class insn_t;
@@ -16,7 +17,16 @@ class RS1 {
         RS1() : _insn(NULL) {}
         //sv_insn_t & operator = (sv_insn_t &i)
         //{ _insn = &i; return i; }
-        operator reg_t () const;
+        operator reg_t () const &;
+};
+
+class RS2 {
+    public:
+        sv_insn_t *_insn;
+        RS2() : _insn(NULL) {}
+        //sv_insn_t & operator = (sv_insn_t &i)
+        //{ _insn = &i; return i; }
+        operator reg_t () const &;
 };
 
 class sv_proc_t
@@ -29,6 +39,7 @@ public:
     processor_t *p;
 
     class RS1 RS1;
+    class RS2 RS2;
 
     class {
         public:
@@ -42,6 +53,7 @@ public:
     void set_insn(sv_insn_t *i) {
         this->insn = *i;
         RS1._insn = i;
+        RS2._insn = i;
     }
 
 #include "sv_insn_decl.h"
-- 
2.30.2