From 09d8726187f3f64ee41ae10345b77d4edf4130c9 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 20 Feb 2020 09:19:44 +0100 Subject: [PATCH] ac: add more ac_gpu_info related shader fields Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/common/ac_gpu_info.c | 29 ++++++++++++++++++++++++++--- src/amd/common/ac_gpu_info.h | 7 +++++++ 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 667070cb2f0..4454f82f4b5 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -666,14 +666,30 @@ bool ac_query_gpu_info(int fd, void *dev_p, /* The number is per SIMD. There is enough SGPRs for the maximum number * of Wave32, which is double the number for Wave64. */ - if (info->chip_class >= GFX10) + if (info->chip_class >= GFX10) { info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2; - else if (info->chip_class >= GFX8) + info->min_sgpr_alloc = 128; + info->sgpr_alloc_granularity = 128; + } else if (info->chip_class >= GFX8) { info->num_physical_sgprs_per_simd = 800; - else + info->min_sgpr_alloc = 16; + info->sgpr_alloc_granularity = 16; + } else { info->num_physical_sgprs_per_simd = 512; + info->min_sgpr_alloc = 8; + info->sgpr_alloc_granularity = 8; + } + + info->max_sgpr_alloc = info->family == CHIP_TONGA || + info->family == CHIP_ICELAND ? 96 : 104; + + info->min_vgpr_alloc = 4; + info->max_vgpr_alloc = 256; + info->vgpr_alloc_granularity = info->chip_class >= GFX10 ? 8 : 4; info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256; + info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4; + return true; } @@ -821,6 +837,13 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd); printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd); printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd); + printf(" num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit); + printf(" min_sgpr_alloc = %i\n", info->min_sgpr_alloc); + printf(" max_sgpr_alloc = %i\n", info->max_sgpr_alloc); + printf(" sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity); + printf(" min_vgpr_alloc = %i\n", info->min_vgpr_alloc); + printf(" max_vgpr_alloc = %i\n", info->max_vgpr_alloc); + printf(" vgpr_alloc_granularity = %i\n", info->vgpr_alloc_granularity); printf("Render backend info:\n"); printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 18c1bb16379..41ecb9603eb 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -153,6 +153,13 @@ struct radeon_info { uint32_t max_wave64_per_simd; uint32_t num_physical_sgprs_per_simd; uint32_t num_physical_wave64_vgprs_per_simd; + uint32_t num_simd_per_compute_unit; + uint32_t min_sgpr_alloc; + uint32_t max_sgpr_alloc; + uint32_t sgpr_alloc_granularity; + uint32_t min_vgpr_alloc; + uint32_t max_vgpr_alloc; + uint32_t vgpr_alloc_granularity; /* Render backends (color + depth blocks). */ uint32_t r300_num_gb_pipes; -- 2.30.2