From 09d9a8913e8c28fc4c1c60d7da85a2f093786894 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 7 Feb 2014 22:22:45 -0800 Subject: [PATCH] i965: Pull format conversion logic out of brw_depthbuffer_format. brw_depthbuffer_format is not very reusable at the moment, since it uses global state (ctx->DrawBuffer) to access a particular depth buffer. For HiZ on Broadwell, I need a function which simply converts the formats. However, at least one existing user of brw_depthbuffer_format really wants the existing interface. So, I've created a new function. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_misc_state.c | 33 +-------------- .../drivers/dri/i965/brw_surface_formats.c | 41 +++++++++++++++++++ 3 files changed, 43 insertions(+), 32 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 98e90e2131f..cf0fe98cd15 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1666,6 +1666,7 @@ void brw_upload_abo_surfaces(struct brw_context *brw, bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format); bool brw_render_target_supported(struct brw_context *brw, struct gl_renderbuffer *rb); +uint32_t brw_depth_format(struct brw_context *brw, mesa_format format); /* brw_performance_monitor.c */ void brw_init_performance_monitors(struct brw_context *brw); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index ca88b940f43..b984d47c4f5 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -150,38 +150,7 @@ brw_depthbuffer_format(struct brw_context *brw) if (!drb) return BRW_DEPTHFORMAT_D32_FLOAT; - switch (drb->mt->format) { - case MESA_FORMAT_Z_UNORM16: - return BRW_DEPTHFORMAT_D16_UNORM; - case MESA_FORMAT_Z_FLOAT32: - return BRW_DEPTHFORMAT_D32_FLOAT; - case MESA_FORMAT_Z24_UNORM_X8_UINT: - if (brw->gen >= 6) { - return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; - } else { - /* Use D24_UNORM_S8, not D24_UNORM_X8. - * - * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM, - * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits - * 3DSTATE_DEPTH_BUFFER.Surface_Format). - * - * However, on Gen5, D24_UNORM_X8 may be used only if separate - * stencil is enabled, and we never enable it. From the Ironlake PRM, - * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable: - * If this field is disabled, the Surface Format of the depth - * buffer cannot be D24_UNORM_X8_UINT. - */ - return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; - } - case MESA_FORMAT_Z24_UNORM_S8_UINT: - return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; - case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: - return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT; - default: - _mesa_problem(ctx, "Unexpected depth format %s\n", - _mesa_get_format_name(intel_rb_format(drb))); - return BRW_DEPTHFORMAT_D16_UNORM; - } + return brw_depth_format(brw, drb->mt->format); } /** diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 6a7e00a5804..b2c36d970ac 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -730,6 +730,47 @@ translate_tex_format(struct brw_context *brw, } } +/** + * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum. + */ +uint32_t +brw_depth_format(struct brw_context *brw, mesa_format format) +{ + switch (format) { + case MESA_FORMAT_Z_UNORM16: + return BRW_DEPTHFORMAT_D16_UNORM; + case MESA_FORMAT_Z_FLOAT32: + return BRW_DEPTHFORMAT_D32_FLOAT; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + if (brw->gen >= 6) { + return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; + } else { + /* Use D24_UNORM_S8, not D24_UNORM_X8. + * + * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM, + * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits + * 3DSTATE_DEPTH_BUFFER.Surface_Format). + * + * However, on Gen5, D24_UNORM_X8 may be used only if separate + * stencil is enabled, and we never enable it. From the Ironlake PRM, + * same section as above, 3DSTATE_DEPTH_BUFFER's + * "Separate Stencil Buffer Enable" bit: + * + * "If this field is disabled, the Surface Format of the depth + * buffer cannot be D24_UNORM_X8_UINT." + */ + return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; + } + case MESA_FORMAT_Z24_UNORM_X8_UINT: + return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT; + default: + assert(!"Unexpected depth format."); + return BRW_DEPTHFORMAT_D32_FLOAT; + } +} + /** Can HiZ be enabled on a depthbuffer of the given format? */ bool brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format) -- 2.30.2