From 09ef279b603fba4377752ef712ab106b547d1fb2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 May 2015 13:10:43 +0200 Subject: [PATCH] Added iCE40 PLL cells --- techlibs/ice40/cells_sim.v | 168 +++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9ae01b0f..473701172 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -672,3 +672,171 @@ module ICESTORM_LC ( assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o; endmodule +// SiliconBlue PLL Cells + +(* blackbox *) +module SB_PLL40_CORE ( + input REFERENCECLK, + output PLLOUTCORE, + output PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + output SDO, + input SDI, + input SCLK +); + parameter FEEDBACK_PATH = "SIMPLE"; + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + parameter SHIFTREG_DIV_MODE = 1'b0; + parameter FDA_FEEDBACK = 4'b0000; + parameter FDA_RELATIVE = 4'b0000; + parameter PLLOUT_SELECT = "GENCLK"; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0000000; + parameter DIVQ = 3'b000; + parameter FILTER_RANGE = 3'b000; + parameter ENABLE_ICEGATE = 1'b0; + parameter TEST_MODE = 1'b0; + parameter EXTERNAL_DIVIDE_FACTOR = 1; +endmodule + +(* blackbox *) +module SB_PLL40_PAD ( + input PACKAGEPIN, + output PLLOUTCORE, + output PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + output SDO, + input SDI, + input SCLK +); + parameter FEEDBACK_PATH = "SIMPLE"; + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + parameter SHIFTREG_DIV_MODE = 1'b0; + parameter FDA_FEEDBACK = 4'b0000; + parameter FDA_RELATIVE = 4'b0000; + parameter PLLOUT_SELECT = "GENCLK"; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0000000; + parameter DIVQ = 3'b000; + parameter FILTER_RANGE = 3'b000; + parameter ENABLE_ICEGATE = 1'b0; + parameter TEST_MODE = 1'b0; + parameter EXTERNAL_DIVIDE_FACTOR = 1; +endmodule + +(* blackbox *) +module SB_PLL40_2_PAD ( + input PACKAGEPIN, + output PLLOUTCOREA, + output PLLOUTGLOBALA, + output PLLOUTCOREB, + output PLLOUTGLOBALB, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + output SDO, + input SDI, + input SCLK +); + parameter FEEDBACK_PATH = "SIMPLE"; + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + parameter SHIFTREG_DIV_MODE = 1'b0; + parameter FDA_FEEDBACK = 4'b0000; + parameter FDA_RELATIVE = 4'b0000; + parameter PLLOUT_SELECT_PORTB = "GENCLK"; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0000000; + parameter DIVQ = 3'b000; + parameter FILTER_RANGE = 3'b000; + parameter ENABLE_ICEGATE_PORTA = 1'b0; + parameter ENABLE_ICEGATE_PORTB = 1'b0; + parameter TEST_MODE = 1'b0; + parameter EXTERNAL_DIVIDE_FACTOR = 1; +endmodule + +(* blackbox *) +module SB_PLL40_2F_CORE ( + input REFERENCECLK, + output PLLOUTCOREA, + output PLLOUTGLOBALA, + output PLLOUTCOREB, + output PLLOUTGLOBALB, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + output SDO, + input SDI, + input SCLK +); + parameter FEEDBACK_PATH = "SIMPLE"; + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + parameter SHIFTREG_DIV_MODE = 1'b0; + parameter FDA_FEEDBACK = 4'b0000; + parameter FDA_RELATIVE = 4'b0000; + parameter PLLOUT_SELECT_PORTA = "GENCLK"; + parameter PLLOUT_SELECT_PORTB = "GENCLK"; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0000000; + parameter DIVQ = 3'b000; + parameter FILTER_RANGE = 3'b000; + parameter ENABLE_ICEGATE_PORTA = 1'b0; + parameter ENABLE_ICEGATE_PORTB = 1'b0; + parameter TEST_MODE = 1'b0; + parameter EXTERNAL_DIVIDE_FACTOR = 1; +endmodule + +(* blackbox *) +module SB_PLL40_2F_PAD ( + input PACKAGEPIN, + output PLLOUTCOREA, + output PLLOUTGLOBALA, + output PLLOUTCOREB, + output PLLOUTGLOBALB, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + output SDO, + input SDI, + input SCLK +); + parameter FEEDBACK_PATH = "SIMPLE"; + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + parameter SHIFTREG_DIV_MODE = 2'b00; + parameter FDA_FEEDBACK = 4'b0000; + parameter FDA_RELATIVE = 4'b0000; + parameter PLLOUT_SELECT_PORTA = "GENCLK"; + parameter PLLOUT_SELECT_PORTB = "GENCLK"; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0000000; + parameter DIVQ = 3'b000; + parameter FILTER_RANGE = 3'b000; + parameter ENABLE_ICEGATE_PORTA = 1'b0; + parameter ENABLE_ICEGATE_PORTB = 1'b0; + parameter TEST_MODE = 1'b0; + parameter EXTERNAL_DIVIDE_FACTOR = 1; +endmodule + -- 2.30.2