From 09fcd8e1491fa20f45b546144e18e201458e925d Mon Sep 17 00:00:00 2001 From: Ramana Radhakrishnan Date: Fri, 11 Sep 2015 09:44:26 +0000 Subject: [PATCH] Remove separate movtf pattern - Use an iterator for all FP modes. movtf is unnecessary as a separate expander. Move this to be with the standard scalar floating point expanders. Achieved by adding a new iterator and then using the same. Tested cross aarch64-none-elf and no regressions. Rebased version from https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00767.html 2015-09-10 Ramana Radhakrishnan PR target/63304 * config/aarch64/aarch.md (mov:GPF_F16): Use GPF_TF_F16. (movtf): Delete. * config/aarch64/iterators.md (GPF_TF_F16): New. (GPF_F16): Delete. From-SVN: r227679 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64.md | 22 ++-------------------- gcc/config/aarch64/iterators.md | 4 ++-- 3 files changed, 12 insertions(+), 22 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3eea5477fbe..5de2845ea62 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-09-10 Ramana Radhakrishnan + + PR target/63304 + * config/aarch64/aarch.md (mov:GPF_F16): Use GPF_TF_F16. + (movtf): Delete. + * config/aarch64/iterators.md (GPF_TF_F16): New. + (GPF_F16): Delete. + 2015-09-10 Nathan Sidwell * config/nvptx/nvptx.c (nvptx_expand_call): Add spacing. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b6a6c343cba..5a005b572c8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1099,8 +1099,8 @@ }) (define_expand "mov" - [(set (match_operand:GPF_F16 0 "nonimmediate_operand" "") - (match_operand:GPF_F16 1 "general_operand" ""))] + [(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "") + (match_operand:GPF_TF_F16 1 "general_operand" ""))] "" { if (!TARGET_FLOAT) @@ -1174,24 +1174,6 @@ f_loadd,f_stored,load1,store1,mov_reg")] ) -(define_expand "movtf" - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "general_operand" ""))] - "" - { - if (!TARGET_FLOAT) - { - aarch64_err_no_fpadvsimd (TFmode, "code"); - FAIL; - } - - if (GET_CODE (operands[0]) == MEM - && ! (GET_CODE (operands[1]) == CONST_DOUBLE - && aarch64_float_const_zero_rtx_p (operands[1]))) - operands[1] = force_reg (TFmode, operands[1]); - } -) - (define_insn "*movtf_aarch64" [(set (match_operand:TF 0 "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 2bd64c897cf..ff698001d68 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -38,8 +38,8 @@ ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) (define_mode_iterator GPF [SF DF]) -;; Iterator for General Purpose Float registers, inc __fp16. -(define_mode_iterator GPF_F16 [HF SF DF]) +;; Iterator for all scalar floating point modes (HF, SF, DF and TF) +(define_mode_iterator GPF_TF_F16 [HF SF DF TF]) ;; Double vector modes. (define_mode_iterator VDF [V2SF V4HF]) -- 2.30.2