From 0a2910d9b0cd766b78a65e43bcb5fc39ef2eabd7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 7 Nov 2018 07:46:44 +0000 Subject: [PATCH] macro-ify rv op elwidth setup/teardown --- riscv/sv_insn_redirect.cc | 105 ++++++++++++++------------------------ 1 file changed, 37 insertions(+), 68 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 7aa0b61..6467e34 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -429,74 +429,43 @@ sv_reg_t (sv_proc_t::zext32)(sv_reg_t const& v) return sv_reg_t(x); } -bool sv_proc_t::rv_int_op_prepare(sv_reg_t const & lhs, sv_reg_t const & rhs, - uint64_t &vlhs, uint64_t &vrhs, - uint8_t &bitwidth) -{ - bitwidth = _insn->src_bitwidth; - if (bitwidth == xlen) { - return true; - } - // sign-extend or zero-extend to max bitwidth of lhs and rhs? - // has the effect of truncating, as well. - if (_insn->signextended) { // sign-extend? - vlhs = sext_bwid(lhs, bitwidth); - vrhs = sext_bwid(rhs, bitwidth); - } else { // nope: zero-extend. - vlhs = zext_bwid(lhs, bitwidth); - vrhs = zext_bwid(rhs, bitwidth); - } - return false; -} - -bool sv_proc_t::rv_int_op_prepare(sv_sreg_t const & lhs, sv_sreg_t const & rhs, - int64_t &vlhs, int64_t &vrhs, - uint8_t &bitwidth) -{ - bitwidth = _insn->src_bitwidth; - if (bitwidth == xlen) { - return true; - } - // sign-extend or zero-extend to max bitwidth of lhs and rhs? - // has the effect of truncating, as well. - if (_insn->signextended) { // sign-extend? - vlhs = sext_bwid(lhs, bitwidth); - vrhs = sext_bwid(rhs, bitwidth); - } else { // nope: zero-extend. - vlhs = zext_bwid(lhs, bitwidth); - vrhs = zext_bwid(rhs, bitwidth); - } - return false; -} - -sv_sreg_t sv_proc_t::rv_int_op_finish(sv_sreg_t const & lhs, - sv_sreg_t const & rhs, - int64_t &result, uint8_t &bitwidth) -{ - if (_insn->signextended) { // sign-extend? - result = sext_bwid(result, bitwidth); - } else { // nope: zero-extend. - result = zext_bwid(result, bitwidth); - } - uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); - fprintf(stderr, "result sext %d wid %d %lx\n", _insn->signextended, - reswidth, result); - return sv_reg_t(result, xlen, reswidth); -} - -sv_reg_t sv_proc_t::rv_int_op_finish(sv_reg_t const & lhs, sv_reg_t const & rhs, - uint64_t &result, uint8_t &bitwidth) -{ - if (_insn->signextended) { // sign-extend? - result = sext_bwid(result, bitwidth); - } else { // nope: zero-extend. - result = zext_bwid(result, bitwidth); - } - uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); - fprintf(stderr, "result sext %d wid %d %lx\n", _insn->signextended, - reswidth, result); - return sv_reg_t(result, xlen, reswidth); -} +#define OP_PREP_FINISH( SLHSTYPE, SRHSTYPE, SRESTYPE, \ + LHSTYPE, RHSTYPE, RESTYPE ) \ +bool sv_proc_t::rv_int_op_prepare(SLHSTYPE const & lhs, SRHSTYPE const & rhs, \ + LHSTYPE &vlhs, RHSTYPE &vrhs, \ + uint8_t &bitwidth) \ +{ \ + bitwidth = _insn->src_bitwidth; \ + if (bitwidth == xlen) { \ + return true; \ + } \ + if (_insn->signextended) { \ + vlhs = sext_bwid(lhs, bitwidth); \ + vrhs = sext_bwid(rhs, bitwidth); \ + } else { \ + vlhs = zext_bwid(lhs, bitwidth); \ + vrhs = zext_bwid(rhs, bitwidth); \ + } \ + return false; \ +} \ +SRESTYPE sv_proc_t::rv_int_op_finish(SLHSTYPE const & lhs, \ + SRHSTYPE const & rhs, \ + RESTYPE &result, uint8_t &bitwidth) \ +{ \ + if (_insn->signextended) { \ + result = sext_bwid(result, bitwidth); \ + } else { \ + result = zext_bwid(result, bitwidth); \ + } \ + uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); \ + fprintf(stderr, "result sext %d wid %d %lx\n", _insn->signextended, \ + reswidth, result); \ + return SRESTYPE(result, xlen, reswidth); \ +} + + +OP_PREP_FINISH(sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t) +OP_PREP_FINISH(sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t) sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) { -- 2.30.2