From 0a47c560d87ed77858a95d4340e8435eef3ba47e Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 12 Apr 2022 20:48:39 +0200 Subject: [PATCH] revert changes in wishbone_bram_wrapper.vhdl --- wishbone_bram_wrapper.vhdl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index fcf528b..ced0431 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -76,7 +76,8 @@ begin bram_re <= ram_re; -- Wishbone interface - ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3); + ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0); + -- not that a wishbone compliant version of libre-soc is needed ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we; ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we; wishbone_out.stall <= '0'; -- 2.30.2