From 0a5d285bb5c557cd7fb3db9642372425562fca68 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 21:53:20 +0100 Subject: [PATCH] testing CRs after writing: not in the right bit-order --- src/soc/simple/test/test_core.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 96abda8d..0cb97a59 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -147,6 +147,20 @@ class TestRunner(FHDLTestCase): self.assertEqual(simregval, intregs[i], "int reg %d not equal %s" % (i, repr(code))) + # CRs + crregs = [] + for i in range(8): + rval = yield core.regs.cr.regs[i].reg + crregs.append(rval) + print ("cr regs", list(map(hex, crregs))) + print ("sim cr reg", hex(cr)) + for i in range(8): + rval = crregs[i] + cri = sim.crl[7-i].get_range().value + print ("cr reg", i, hex(cri), i, hex(rval)) + self.assertEqual(cri, rval, + "cr reg %d not equal %s" % (i, repr(code))) + sim.add_sync_process(process) with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw", traces=[]): -- 2.30.2