From 0a844541d47004ede50ccb14433450b323a85ce7 Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Tue, 25 Jun 2019 15:51:52 +0000
Subject: [PATCH] =?utf8?q?vendor.xilinx=5F{spartan6,7series}:=20speedgrade?=
 =?utf8?q?=E2=86=92speed.?=
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For consistency with ECP5.
---
 nmigen/vendor/xilinx_7series.py  | 8 ++++----
 nmigen/vendor/xilinx_spartan6.py | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index a9836d9..b711be0 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -42,9 +42,9 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         * ``{{name}}.bit``: binary bitstream.
     """
 
-    device = abstractproperty()
+    device  = abstractproperty()
     package = abstractproperty()
-    speedgrade = abstractproperty()
+    speed   = abstractproperty()
 
     file_templates = {
         **TemplatedPlatform.build_script_templates,
@@ -54,7 +54,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}
-            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
+            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
             {% for file in platform.extra_files %}
                 {% if file.endswith((".v", ".sv")) -%}
                     add_files {{file}}
@@ -63,7 +63,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             add_files {{name}}.v
             read_xdc {{name}}.xdc
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
-            synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
+            synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
             report_timing_summary -file {{name}}_timing_synth.rpt
             report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index 8158488..fef9461 100644
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -45,9 +45,9 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         * ``{{name}}.bit``: binary bitstream.
     """
 
-    device     = abstractproperty()
-    package    = abstractproperty()
-    speedgrade = abstractproperty()
+    device  = abstractproperty()
+    package = abstractproperty()
+    speed   = abstractproperty()
 
     file_templates = {
         **TemplatedPlatform.build_script_templates,
@@ -70,7 +70,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
             -ifn {{name}}.prj
             -ofn {{name}}.ngc
             -top {{name}}
-            -p {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
+            -p {{platform.device}}{{platform.package}}-{{platform.speed}}
             {{get_override("script_after_run")|default("# (script_after_run placeholder)")}}
         """,
         "{{name}}.ucf": r"""
-- 
2.30.2