From 0a91c086b8649a65befa3fdf3ef8460761bb87aa Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Thu, 26 Mar 2020 17:30:16 +0100 Subject: [PATCH] aco: Extract store_output_to_temps into a separate function. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Will be used by LS output stores. Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- .../compiler/aco_instruction_selection.cpp | 53 +++++++++++-------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index c2da6d6e238..b8816f51cde 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -3302,6 +3302,33 @@ bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr return false; } +bool store_output_to_temps(isel_context *ctx, nir_intrinsic_instr *instr) +{ + unsigned write_mask = nir_intrinsic_write_mask(instr); + unsigned component = nir_intrinsic_component(instr); + unsigned idx = nir_intrinsic_base(instr) + component; + + nir_instr *off_instr = instr->src[1].ssa->parent_instr; + if (off_instr->type != nir_instr_type_load_const) + return false; + + Temp src = get_ssa_temp(ctx, instr->src[0].ssa); + idx += nir_src_as_uint(instr->src[1]) * 4u; + + if (instr->src[0].ssa->bit_size == 64) + write_mask = widen_mask(write_mask, 2); + + for (unsigned i = 0; i < 8; ++i) { + if (write_mask & (1 << i)) { + ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u); + ctx->outputs.temps[idx] = emit_extract_vector(ctx, src, i, v1); + } + idx++; + } + + return true; +} + void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr) { Builder bld(ctx->program, ctx->block); @@ -3421,28 +3448,12 @@ void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr) ctx->stage == tess_eval_vs || ctx->stage == fragment_fs || ctx->shader->info.stage == MESA_SHADER_GEOMETRY) { - unsigned write_mask = nir_intrinsic_write_mask(instr); - unsigned component = nir_intrinsic_component(instr); - Temp src = get_ssa_temp(ctx, instr->src[0].ssa); - unsigned idx = nir_intrinsic_base(instr) + component; - - nir_instr *off_instr = instr->src[1].ssa->parent_instr; - if (off_instr->type != nir_instr_type_load_const) { - fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n"); - nir_print_instr(off_instr, stderr); + bool stored_to_temps = store_output_to_temps(ctx, instr); + if (!stored_to_temps) { + fprintf(stderr, "Unimplemented output offset instruction:\n"); + nir_print_instr(instr->src[1].ssa->parent_instr, stderr); fprintf(stderr, "\n"); - } - idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u; - - if (instr->src[0].ssa->bit_size == 64) - write_mask = widen_mask(write_mask, 2); - - for (unsigned i = 0; i < 8; ++i) { - if (write_mask & (1 << i)) { - ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u); - ctx->outputs.temps[idx] = emit_extract_vector(ctx, src, i, v1); - } - idx++; + abort(); } } else if (ctx->stage == vertex_es || ctx->stage == vertex_ls || -- 2.30.2