From 0aa3c339ccfddad71657060448c72a3144879311 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 16:33:14 +0200 Subject: [PATCH] targets/genesys2: set cmd_latency to 1. --- litex/boards/targets/genesys2.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 8557c0c5..d0b33def 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -56,7 +56,8 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq) + sys_clk_freq = sys_clk_freq, + cmd_latency = 1) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, -- 2.30.2