From 0ab7d6f437f2f7a1b2d84f30497f3c2013b52791 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 17 Jun 2011 18:24:56 -0700 Subject: [PATCH] i965/gen6: Limit the workaround flush to once per primitive. We're about to call this function in a bunch of state emits, so let's not spam the hardware with flushes too hard. --- src/mesa/drivers/dri/i965/brw_context.c | 2 ++ src/mesa/drivers/dri/i965/brw_draw.c | 2 ++ src/mesa/drivers/dri/i965/brw_vtbl.c | 5 +++++ src/mesa/drivers/dri/intel/intel_batchbuffer.c | 5 +++++ src/mesa/drivers/dri/intel/intel_context.h | 2 ++ 5 files changed, 16 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index d6a99ab06e2..636821839a1 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -240,6 +240,8 @@ GLboolean brwCreateContext( int api, brw->emit_state_always = 0; + intel->batch.need_workaround_flush = true; + ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 6144f0a2bce..350fc51a8a1 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -177,6 +177,8 @@ static void brw_emit_prim(struct brw_context *brw, OUT_BATCH(base_vertex_location); ADVANCE_BATCH(); + intel->batch.need_workaround_flush = true; + if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel); } diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 0f731482629..8612e743265 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -118,6 +118,11 @@ static void brw_new_batch( struct intel_context *intel ) */ brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH; + /* Assume that the last command before the start of our batch was a + * primitive, for safety. + */ + intel->batch.need_workaround_flush = true; + brw->vb.nr_current_buffers = 0; /* Mark that the current program cache BO has been used by the GPU. diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 9e8f8b5eefd..77563aefdc5 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -296,6 +296,9 @@ emit: static void intel_emit_post_sync_nonzero_flush(struct intel_context *intel) { + if (!intel->batch.need_workaround_flush) + return; + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); @@ -303,6 +306,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0); OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); + + intel->batch.need_workaround_flush = false; } /* Emit a pipelined flush to either flush render and texture cache for diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 751af459e9c..148fb0c2c9a 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -183,6 +183,8 @@ struct intel_context drm_intel_bo *last_bo; /** BO for post-sync nonzero writes for gen6 workaround. */ drm_intel_bo *workaround_bo; + bool need_workaround_flush; + struct cached_batch_item *cached_items; uint16_t emit, total; -- 2.30.2