From 0acaedc92d1697bfe61b2834aea6332b5b095b77 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 9 Feb 2020 18:25:20 +0000 Subject: [PATCH] give a_bit proper name, make reset_less --- src/ieee754/part_mul_add/adder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py index c2e75257..2e504368 100644 --- a/src/ieee754/part_mul_add/adder.py +++ b/src/ieee754/part_mul_add/adder.py @@ -204,7 +204,7 @@ class PartitionedAdder(Elaboratable): pi = i/self.pmul # double the range of the partition point test if pi.is_integer() and pi in self.part_pts: # add extra bit set to 0 + 0 for enabled partition points - a_bit = Signal() + a_bit = Signal(name="a_bit_%d" % i, reset_less=True) carry_in = self.carry_in[carry_bit] # convenience m.d.comb += a_bit.eq(self.part_pts[pi].implies(carry_in)) # and 1 + 0 for disabled partition points -- 2.30.2