From 0afb5e8aee35febe485ae89eddea2292c79685a1 Mon Sep 17 00:00:00 2001 From: Aleksandar Kostovic Date: Thu, 14 Feb 2019 15:37:57 +0100 Subject: [PATCH] Translate put_z verilog case into nmigen --- src/add/nmigen_add_experiment.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 24e87428..a69b77b2 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -330,17 +330,16 @@ class FPADD: # ****** # put_z stage - """ - put_z: - begin - s_out_z_stb <= 1; - s_out_z <= z; - if (s_out_z_stb && out_z_ack) begin - s_out_z_stb <= 0; - state <= get_a; - end - end - """ + with m.State("put_z"): + m.next = "get_a" + m.d.sync += [ + s_out_z_stb.eq(1), + s_out_z.eq(z) + ] + with m.If(s_out_z_stb & out_z_ack): + m.d.sync += [ + s_out_z_stb.eq(0) + ] return m -- 2.30.2