From 0b0958504c29b58c4005246f4ca5d7597396272b Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 10 Jul 2020 18:32:32 +0200 Subject: [PATCH] Fix DDR3 module parameter --- examples/headless-ecpix5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py index a7e4867..14733c5 100644 --- a/examples/headless-ecpix5.py +++ b/examples/headless-ecpix5.py @@ -185,7 +185,7 @@ class DDR3SoC(SoC, Elaboratable): self.ddrphy = ECP5DDRPHY(platform.request("ddr3", 0)) self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) - ddrmodule = MT41K256M16(clk_freq, "1:4") + ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2") self.dramcore = gramCore( phy=self.ddrphy, -- 2.30.2