From 0b09b0e015ef54c7c74387d98192b81cee215bbd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 2 Mar 2019 11:09:44 +0000 Subject: [PATCH] add1 module setup reorg --- src/add/nmigen_add_experiment.py | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 2ea78985..31051211 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -475,14 +475,6 @@ class FPAddStage1Mod(FPState): self.out_z = FPNumBase(width, False) self.out_of = Overflow() - def setup(self, m, in_tot, in_z, out_z, out_of): - """ links module to inputs and outputs - """ - m.d.comb += self.in_z.copy(in_z) - m.d.comb += self.in_tot.eq(in_tot) - #m.d.comb += out_z.copy(self.out_z) - #m.d.comb += out_of.copy(self.out_of) - def elaborate(self, platform): m = Module() #m.submodules.norm1_in_overflow = self.in_of @@ -521,6 +513,16 @@ class FPAddStage1(FPState): self.out_of = Overflow() self.norm_stb = Signal() + def setup(self, m, in_tot, in_z): + """ links module to inputs and outputs + """ + m.submodules.add1 = self.mod + + m.d.comb += self.mod.in_z.copy(in_z) + m.d.comb += self.mod.in_tot.eq(in_tot) + + m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state + def action(self, m): m.submodules.add1_out_overflow = self.out_of m.d.sync += self.out_of.copy(self.mod.out_of) @@ -825,14 +827,10 @@ class FPADD: m.submodules.align = alm.mod add0 = self.add_state(FPAddStage0(self.width)) - add0.set_inputs({"a": alm.out_a, "b": alm.out_b}) add0.setup(m, alm.out_a, alm.out_b) add1 = self.add_state(FPAddStage1(self.width)) - #add1.set_outputs({"z": az}) # XXX Z as output - add1.mod.setup(m, add0.out_tot, add0.out_z, None, add1.out_of) - m.submodules.add1 = add1.mod - m.d.sync += add1.norm_stb.eq(0) # sets to zero when not in add1 state + add1.setup(m, add0.out_tot, add0.out_z) az = add1.out_z -- 2.30.2