From 0b21a74f4e08686f2a472d3575392ce86b69f28e Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Thu, 17 Jan 2019 05:23:06 +0000
Subject: [PATCH] hdl.ast: allow sampling ClockSignal, ResetSignal.

---
 nmigen/hdl/ast.py           | 2 +-
 nmigen/hdl/xfrm.py          | 4 ++++
 nmigen/test/test_hdl_ast.py | 6 ++++--
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index 4b41381..735f412 100644
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -844,7 +844,7 @@ class Sample(Value):
         self.value  = Value.wrap(expr)
         self.clocks = int(clocks)
         self.domain = domain
-        if not isinstance(self.value, (Const, Signal)):
+        if not isinstance(self.value, (Const, Signal, ClockSignal, ResetSignal)):
             raise TypeError("Sampled value may only be a signal or a constant, not {!r}"
                             .format(self.value))
         if self.clocks < 0:
diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py
index 40ce767..473139b 100644
--- a/nmigen/hdl/xfrm.py
+++ b/nmigen/hdl/xfrm.py
@@ -364,6 +364,10 @@ class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
             return "c${}".format(value.value), value.value
         elif isinstance(value, Signal):
             return "s${}".format(value.name), value.reset
+        elif isinstance(value, ClockSignal):
+            return "clk", 0
+        elif isinstance(value, ResetSignal):
+            return "rst", 1
         else:
             raise NotImplementedError # :nocov:
 
diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py
index 1aee24b..d1c5bb5 100644
--- a/nmigen/test/test_hdl_ast.py
+++ b/nmigen/test/test_hdl_ast.py
@@ -504,8 +504,10 @@ class SampleTestCase(FHDLTestCase):
         self.assertEqual(s.shape(), (1, False))
 
     def test_signal(self):
-        s = Sample(Signal(2), 1, "sync")
-        self.assertEqual(s.shape(), (2, False))
+        s1 = Sample(Signal(2), 1, "sync")
+        self.assertEqual(s1.shape(), (2, False))
+        s2 = Sample(ClockSignal(), 1, "sync")
+        s3 = Sample(ResetSignal(), 1, "sync")
 
     def test_wrong_value_operator(self):
         with self.assertRaises(TypeError,
-- 
2.30.2