From 0b7dc18b6f8205c0ae21f18713c66c374163614a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 22 Sep 2020 22:47:02 +0100 Subject: [PATCH] add 2 PWMs (quick, easy to do) --- src/soc/litex/florent/libresoc/ls180.py | 2 ++ src/soc/litex/florent/ls180soc.py | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index bcf363b5..ce99735e 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -87,6 +87,8 @@ _io = [ Misc("SLEWRATE=FAST"), ), + ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")), + ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")), ] if False: diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 4f4b3d24..877abf02 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -22,6 +22,7 @@ from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut#, GPIOTristate from litex.soc.cores.spi import SPIMaster +from litex.soc.cores.pwm import PWM from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings @@ -198,6 +199,13 @@ class LibreSoCSim(SoCCore): self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi) self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo) + # PWM + for i in range(2): + name = "pwm%d" % i + setattr(self.submodules, name, PWM(platform.request("pwm", i))) + self.add_csr(name) + + # Debug --------------------------------------------------------------- if not debug: return -- 2.30.2