From 0b84adbe477a4efd4edc14751813e5d3e303700d Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Thu, 31 Dec 2020 17:28:05 -0300 Subject: [PATCH] Sign extend the second input port --- src/soc/experiment/alu_hier.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 8a3c70d1..49b0db62 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -224,7 +224,12 @@ class ALU(Elaboratable): mod.a.eq(self.a), mod.b.eq(self.b), ] - m.d.comb += ext_sign.a.eq(self.a) + # EXTS sign extends the first input + with m.If(self.op.insn_type == MicrOp.OP_EXTS): + m.d.comb += ext_sign.a.eq(self.a) + # EXTSWSLI sign extends the second input + with m.Elif(self.op.insn_type == MicrOp.OP_EXTSWSLI): + m.d.comb += ext_sign.a.eq(self.b) # pass invert (and carry later) m.d.comb += add.invert_in.eq(self.op.invert_in) @@ -267,6 +272,8 @@ class ALU(Elaboratable): m.d.sync += alu_r.eq(shf.o) with m.Elif(self.op.insn_type == MicrOp.OP_EXTS): m.d.sync += alu_r.eq(ext_sign.o) + with m.Elif(self.op.insn_type == MicrOp.OP_EXTSWSLI): + m.d.sync += alu_r.eq(ext_sign.o) # SUB is zero-delay, no need to register # NOTE: all of these are fake, just something to test @@ -283,6 +290,9 @@ class ALU(Elaboratable): # EXTS to take 1 with m.Elif(self.op.insn_type == MicrOp.OP_EXTS): m.d.sync += self.counter.eq(1) + # EXTSWSLI to take 1 + with m.Elif(self.op.insn_type == MicrOp.OP_EXTSWSLI): + m.d.sync += self.counter.eq(1) # others to take no delay with m.Else(): m.d.comb += go_now.eq(1) @@ -546,6 +556,8 @@ def test_alu_parallel(): yield from send(13, 2, MicrOp.OP_EXTS) # sign extend -128 (8 bits) yield from send(0x80, 2, MicrOp.OP_EXTS) + # sign extend -128 (8 bits) + yield from send(2, 0x80, MicrOp.OP_EXTSWSLI) def consumer(): # receive and check results, interspersed with wait states @@ -580,6 +592,9 @@ def test_alu_parallel(): # sign extend -128 (8 bits) = -128 (16 bits) result = yield from receive() assert (result == 0xFF80) + # sign extend -128 (8 bits) = -128 (16 bits) + result = yield from receive() + assert (result == 0xFF80) sim.add_sync_process(producer) sim.add_sync_process(consumer) -- 2.30.2