From 0b867bede7180aae5e702119ee4cb6b0d86f7fd8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 15 May 2021 18:02:14 +0100 Subject: [PATCH] add fnabs unit test --- openpower/isa/fpmove.mdwn | 2 +- src/openpower/decoder/isa/test_caller_fp.py | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn index 5247e834..75d3741d 100644 --- a/openpower/isa/fpmove.mdwn +++ b/openpower/isa/fpmove.mdwn @@ -41,7 +41,7 @@ X-Form Pseudo-code: - FRT[0] <- 0b1 || FRB[1:63] + FRT <- 0b1 || FRB[1:63] Special Registers Altered: diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py index d677be4f..3fff1dfb 100644 --- a/src/openpower/decoder/isa/test_caller_fp.py +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -99,10 +99,14 @@ class DecoderTestCase(FHDLTestCase): def test_fp_abs(self): """>>> lst = ["fabs 3, 1", "fabs 4, 2", + "fnabs 5, 1", + "fnabs 6, 2", ] """ lst = ["fabs 3, 1", "fabs 4, 2", + "fnabs 5, 1", + "fnabs 6, 2", ] fprs = [0] * 32 @@ -111,14 +115,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print("FPR 1", sim.fpr(1)) - print("FPR 2", sim.fpr(2)) - print("FPR 3", sim.fpr(3)) - print("FPR 4", sim.fpr(4)) self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64)) self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64)) self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(5), SelectableInt(0xC040266660000000, 64)) + self.assertEqual(sim.fpr(6), SelectableInt(0xC040266660000000, 64)) def run_tst_program(self, prog, initial_regs=None, initial_mem=None, -- 2.30.2