From 0ba9ab92b4fc9a6e9830843d11ef94d0a5df5b89 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Aug 2019 16:19:22 +0200 Subject: [PATCH] altera/common: fix AsyncResetSynchronizer polarity and simplify --- litex/build/altera/common.py | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py index 288e7184..d2d56d88 100644 --- a/litex/build/altera/common.py +++ b/litex/build/altera/common.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # This file is Copyright (c) 2019 vytautasb # License: BSD @@ -48,20 +48,17 @@ class AlteraDifferentialOutput: class AlteraAsyncResetSynchronizerImpl(Module): def __init__(self, cd, async_reset): - if not hasattr(async_reset, "attr"): - i, async_reset = async_reset, Signal() - self.comb += async_reset.eq(i) rst_meta = Signal() self.specials += [ Instance("DFF", - i_d=0, i_clk=cd.clk, i_clrn=1, - i_prn=async_reset, o_q=rst_meta, - attr={"async_reg", "ars_ff1"} + i_d=0, i_clk=cd.clk, + i_clrn=1, i_prn=~async_reset, + o_q=rst_meta ), Instance("DFF", - i_d=rst_meta, i_clk=cd.clk, i_clrn=1, - i_prn=async_reset, o_q=cd.rst, - attr={"async_reg", "ars_ff2"} + i_d=rst_meta, i_clk=cd.clk, + i_clrn=1, i_prn=~async_reset, + o_q=cd.rst ) ] -- 2.30.2