From 0babe500e0ff03c6831e2a64691725e8dc7ddb3d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Jun 2020 19:21:20 +0100 Subject: [PATCH] move debug statements to check function --- src/soc/simple/test/test_core.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 0afe5556..7e13dfe8 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -33,6 +33,7 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase def setup_regs(core, test): + # set up INT regfile, "direct" write (bypass rd/write ports) intregs = core.regs.int for i in range(32): @@ -69,6 +70,16 @@ def setup_regs(core, test): yield xregs.regs[xregs.OV].reg.eq(0) yield xregs.regs[xregs.CA].reg.eq(0) + # XER + so = yield xregs.regs[xregs.SO].reg + ov = yield xregs.regs[xregs.OV].reg + ca = yield xregs.regs[xregs.CA].reg + oe = yield pdecode2.e.oe.oe + oe_ok = yield pdecode2.e.oe.oe_ok + + print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca)) + print ("oe:", oe, oe_ok) + def check_regs(dut, sim, core, test, code): # int regs @@ -198,17 +209,6 @@ class TestRunner(FHDLTestCase): #fuval = self.funit.value #self.assertEqual(fn_unit & fuval, fuval) - # XER - xregs = core.regs.xer - so = yield xregs.regs[xregs.SO].reg - ov = yield xregs.regs[xregs.OV].reg - ca = yield xregs.regs[xregs.CA].reg - oe = yield pdecode2.e.oe.oe - oe_ok = yield pdecode2.e.oe.oe_ok - - print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca)) - print ("oe:", oe, oe_ok) - # set operand and get inputs yield from set_issue(core, pdecode2, sim) yield Settle() -- 2.30.2