From 0bc1cd6f777b7af91fda966513fcb64d7465437a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 May 2014 16:11:32 +0200 Subject: [PATCH] fix uart selection when opening wishbone --- miscope/host/uart2wishbone.py | 4 ++-- miscope/host/vcd.py | 12 +++++++++++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py index ca4e5874..df79a1a1 100644 --- a/miscope/host/uart2wishbone.py +++ b/miscope/host/uart2wishbone.py @@ -23,13 +23,13 @@ class Uart2Wishbone: self.uart.open() self.uart.flushInput() try: - wb.regs.uart2wb_sel.write(1) + self.regs.uart2wb_sel.write(1) except: pass def close(self): try: - wb.regs.uart2wb_sel.write(0) + self.regs.uart2wb_sel.write(0) except: pass self.uart.close() diff --git a/miscope/host/vcd.py b/miscope/host/vcd.py index 4b2bad8a..0259e609 100644 --- a/miscope/host/vcd.py +++ b/miscope/host/vcd.py @@ -1,7 +1,17 @@ import sys import datetime -from miscope.std.misc import * +def dec2bin(d, nb=0): + if d=="x": + return "x"*nb + elif d==0: + b="0" + else: + b="" + while d!=0: + b="01"[d&1]+b + d=d>>1 + return b.zfill(nb) def get_bits(values, width, low, high=None): r = [] -- 2.30.2