From 0bc7e254de03c01ed30e96903ee675fd49753811 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 2 Sep 2022 18:06:15 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5eb0a5716..47c3c8712 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -161,7 +161,8 @@ With element-width overrides being meaningless for Condition
 Register Fields, bits 4 thru 7 of SVP64 RM may be used for additional
 Mode bits.
 
-SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
+SVP64 RM `MODE` (includes repurposing `ELWIDTH` bits 4:5,
+and `ELWIDTH_SRC` bits 6-7 for *alternate* uses) for Branch
 Conditional:
 
 | 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 |  21 | 22  23 |  description     |
-- 
2.30.2