From 0bccfb2994d307601ceba5c3a6223b7ca7cf5338 Mon Sep 17 00:00:00 2001
From: Jim Wilson <jimw@sifive.com>
Date: Thu, 22 Feb 2018 11:28:51 -0800
Subject: [PATCH] RISC-V: Make disassebler work for --enable-targets=all
 config.

	opcodes/
	* disassemble.c (ARCH_riscv): Define if ARCH_all.
---
 opcodes/ChangeLog     | 4 ++++
 opcodes/disassemble.c | 1 +
 2 files changed, 5 insertions(+)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b4b4cbb0c11..325972faeb8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-02-22  Shea Levy <shea@shealevy.com>
+
+	* disassemble.c (ARCH_riscv): Define if ARCH_all.
+
 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-opc.tbl: Add {rex},
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index ae48f5367b0..78f09954630 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -76,6 +76,7 @@
 #define ARCH_pj
 #define ARCH_powerpc
 #define ARCH_pru
+#define ARCH_riscv
 #define ARCH_rs6000
 #define ARCH_rl78
 #define ARCH_rx
-- 
2.30.2