From 0bd45f96b9412ef0092433aa6b70c6ae6839484e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Fri, 22 Feb 2019 22:05:07 +0100 Subject: [PATCH] nir: Use SM5 properties to optimize shift(a@32, iand(31, b)) This is a common pattern from HLSL->SPIRV translation and supported in HW by all current NIR backends. vkpipeline-db results anv (SKL): total instructions in shared programs: 6403130 -> 6402380 (-0.01%) instructions in affected programs: 204084 -> 203334 (-0.37%) helped: 208 HURT: 0 total cycles in shared programs: 1915629582 -> 1918198408 (0.13%) cycles in affected programs: 1158892682 -> 1161461508 (0.22%) helped: 107 HURT: 86 shader-db results on i965 (KBL): total instructions in shared programs: 15284592 -> 15284568 (<.01%) instructions in affected programs: 81683 -> 81659 (-0.03%) helped: 24 HURT: 0 total cycles in shared programs: 375013622 -> 375013932 (<.01%) cycles in affected programs: 40169618 -> 40169928 (<.01%) helped: 13 HURT: 9 Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_opt_algebraic.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index ba27d702b5d..4d01f110f80 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebraic.py @@ -552,6 +552,11 @@ optimizations = [ (('ine', ('ineg', ('b2i', 'a@1')), -1), ('inot', a)), (('iand', ('ineg', ('b2i', a)), 1.0), ('b2f', a)), + # SM5 32-bit shifts are defined to use the 5 least significant bits + (('ishl', 'a@32', ('iand', 31, b)), ('ishl', a, b)), + (('ishr', 'a@32', ('iand', 31, b)), ('ishr', a, b)), + (('ushr', 'a@32', ('iand', 31, b)), ('ushr', a, b)), + # Conversions (('i2b32', ('b2i', 'a@32')), a), (('f2i', ('ftrunc', a)), ('f2i', a)), -- 2.30.2