From 0bdf3144c614aaf34efe63ec563c13bc9cd7bff6 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 22 Aug 1996 07:06:13 +0000 Subject: [PATCH] * v850-opc.c (v850_opcodes): Fix order of displacement and register for "set1", "clr1", "not1", and "tst1". --- opcodes/ChangeLog | 5 +++++ opcodes/v850-opc.c | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 164b1353675..1cf2e84187a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,9 @@ start-sanitize-v850 +Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Fix order of displacement + and register for "set1", "clr1", "not1", and "tst1". + Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) * v850-opc.c (v850_operands): Add "B3" support. diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index d3cac6318d9..0bdfd470085 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -193,10 +193,10 @@ const struct v850_opcode v850_opcodes[] = { { "jr", one(0x0780), one(0xffe0), { D22 } }, /* bit manipulation instructions */ -{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, -{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, -{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, -{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, +{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, +{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, +{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, +{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, /* special instructions */ { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} }, -- 2.30.2