From 0be1dc25cf72da49fc767f2cd6560f738c0449e0 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Mon, 1 Jan 2018 04:20:41 +0100 Subject: [PATCH] r600: increase number of ubos by one to 14 Ideally we'd support 16 (d3d11 requires 15, and mesa subtracts one for non-ubo constants), but that's kind of impossible (it would be only doable if either we'd somehow merge the mesa non-ubo constants with the driver constants, or only use the driver constants with vtx fetch instead of through the kcache mechanism - the latter probably wouldn't be too bad). For now just do as the comment already said, place the gs ring (not really a const buffer in any case) which is only ever referred to through vc fetch clauses at index 16. Throw in a couple asserts for good measure to make sure the hw limit isn't exceeded. Tested-by: Konstantin Kharlamov Reviewed-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 1 + src/gallium/drivers/r600/r600_asm.c | 1 + src/gallium/drivers/r600/r600_pipe.h | 10 ++++++---- src/gallium/drivers/r600/r600_state.c | 1 + 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 81b7c4a2853..f5b8e7115df 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2168,6 +2168,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, va = rbuffer->gpu_address + cb->buffer_offset; if (!gs_ring_buffer) { + assert(buffer_index < R600_MAX_HW_CONST_BUFFERS); radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4, DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags); radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8, diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 69b2d142c15..d6bd561f01f 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -1008,6 +1008,7 @@ static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc, continue; bank = alu->src[i].kc_bank; + assert(bank < R600_MAX_HW_CONST_BUFFERS); line = (sel-512)>>4; index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index e042edf2b40..cb84bc1998a 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -69,11 +69,12 @@ #define R600_MAX_DRAW_CS_DWORDS 58 #define R600_MAX_PFP_SYNC_ME_DWORDS 16 -#define R600_MAX_USER_CONST_BUFFERS 13 +#define EG_MAX_ATOMIC_BUFFERS 8 + +#define R600_MAX_USER_CONST_BUFFERS 14 #define R600_MAX_DRIVER_CONST_BUFFERS 3 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS) - -#define EG_MAX_ATOMIC_BUFFERS 8 +#define R600_MAX_HW_CONST_BUFFERS 16 /* start driver buffers after user buffers */ #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) @@ -84,7 +85,8 @@ #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) /* * Note GS doesn't use a constant buffer binding, just a resource index, - * so it's fine to have it exist at index 16. + * so it's fine to have it exist at index 16. I.e. it's not actually + * a const buffer, just a buffer resource. */ #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 253ff57a98f..89cf7d2e50a 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1712,6 +1712,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, offset = cb->buffer_offset; if (!gs_ring_buffer) { + assert(buffer_index < R600_MAX_HW_CONST_BUFFERS); radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, DIV_ROUND_UP(cb->buffer_size, 256)); radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); -- 2.30.2