From 0beb6a640efd8fed1f11ee5cbb333fbdc5207fbf Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 16 Jul 2020 15:21:24 +0200 Subject: [PATCH] Backport modifications from example's CRG --- gram/simulation/crg.py | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/gram/simulation/crg.py b/gram/simulation/crg.py index d1ce6db..deab928 100644 --- a/gram/simulation/crg.py +++ b/gram/simulation/crg.py @@ -45,10 +45,7 @@ class PLL(Elaboratable): p_CLKOP_TRIM_DELAY=0, p_CLKOS_TRIM_POL="FALLING", p_CLKOS_TRIM_DELAY=0, - p_CLKOP_CPHASE=2, - p_CLKOS_CPHASE=23, i_CLKI=self.clkin, - i_CLKFB=clkfb, i_RST=0, i_STDBY=0, i_PHASESEL0=0, @@ -69,14 +66,6 @@ class PLL(Elaboratable): ) m = Module() m.submodules += pll - with m.If(self.clksel == 0): - m.d.comb += clkfb.eq(self.clkout1) - with m.Elif(self.clksel == 1): - m.d.comb += clkfb.eq(self.clkout2) - with m.Elif(self.clksel == 2): - m.d.comb += clkfb.eq(self.clkout3) - with m.Else(): - m.d.comb += clkfb.eq(self.clkout4) return m @@ -109,7 +98,7 @@ class ECPIX5CRG(Elaboratable): pod_done = Signal() with m.If(podcnt != 0): m.d.rawclk += podcnt.eq(podcnt-1) - m.d.comb += pod_done.eq(podcnt == 0) + m.d.rawclk += pod_done.eq(podcnt == 0) # Generating sync2x (200Mhz) and init (25Mhz) from clk100 cd_sync2x = ClockDomain("sync2x", local=False) -- 2.30.2