From 0bfa3b3e9629d81a5e31c1b91fd25eab734804fa Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 23 May 2012 13:48:51 -0400
Subject: [PATCH] radeon/llvm: Remove AMDIL ROUND_POSINF instruction

---
 src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl | 2 +-
 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 7 +++++++
 src/gallium/drivers/radeon/AMDILInstructions.td   | 2 --
 src/gallium/drivers/radeon/R600Instructions.td    | 5 ++---
 4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index d346f8ca571..654f24f17e5 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -54,7 +54,7 @@ my $FILE_TYPE = $ARGV[0];
 
 open AMDIL, '<', 'AMDILInstructions.td';
 
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'ROUND_POSINF_f32', 'ROUND_NEAREST_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'ROUND_NEAREST_f32');
 
 while (<AMDIL>) {
   if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index ced949ed3d5..1a4c0c4cbca 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -26,6 +26,11 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
 
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+
+  // Library functions.  These default to Expand, but we have instructions
+  // for them.
+  setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
+
 }
 
 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
@@ -74,6 +79,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     case AMDGPUIntrinsic::AMDGPU_umin:
       return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
                                                   Op.getOperand(2));
+    case AMDGPUIntrinsic::AMDIL_round_posinf:
+      return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
   }
 }
 
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index f7bf31f6c60..76a238d4d0e 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -219,8 +219,6 @@ defm ROUND_NEAREST : UnaryIntrinsicFloat<IL_OP_ROUND_NEAR,
           int_AMDIL_round_nearest>;
 defm ROUND_NEGINF : UnaryIntrinsicFloat<IL_OP_ROUND_NEG_INF,
           int_AMDIL_round_neginf>;
-defm ROUND_POSINF : UnaryIntrinsicFloat<IL_OP_ROUND_POS_INF,
-          int_AMDIL_round_posinf>;
 defm ROUND_ZERO : UnaryIntrinsicFloat<IL_OP_ROUND_ZERO,
           int_AMDIL_round_zero>;
 defm ACOS : UnaryIntrinsicFloatScalar<IL_OP_ACOS, int_AMDIL_acos>;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 670598fc31d..e64d499e355 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -368,9 +368,8 @@ def TRUNC : R600_1OP <
 
 def CEIL : R600_1OP <
   0x12, "CEIL",
-  [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
-  let AMDILOp = AMDILInst.ROUND_POSINF_f32;
-}
+  [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
+>;
 
 def RNDNE : R600_1OP <
   0x13, "RNDNE",
-- 
2.30.2