From 0bff8eb210fedd89baed36ecab3608bb259ff520 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Tue, 22 May 2012 11:38:04 -0500
Subject: [PATCH] X86 Regression: update stats due to cc register split

---
 .../ref/x86/linux/pc-o3-timing/config.ini     |    6 +-
 .../ref/x86/linux/pc-o3-timing/simout         |   12 +-
 .../ref/x86/linux/pc-o3-timing/stats.txt      | 1498 ++++++++---------
 .../pc-o3-timing/system.pc.com_1.terminal     |    2 +-
 .../config.ini                                |    6 +-
 .../ruby.stats                                |   34 +-
 .../simout                                    |   10 +-
 .../stats.txt                                 |   18 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +-
 .../se/00.gzip/ref/x86/linux/o3-timing/simout |   10 +-
 .../00.gzip/ref/x86/linux/o3-timing/stats.txt |  895 +++++-----
 .../ref/x86/linux/simple-atomic/config.ini    |    2 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   14 +-
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |    4 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/simout  |   13 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  |  919 +++++-----
 .../ref/x86/linux/simple-atomic/config.ini    |    4 +-
 .../10.mcf/ref/x86/linux/simple-atomic/simout |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../10.mcf/ref/x86/linux/simple-timing/simout |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   14 +-
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |   37 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  957 +++++------
 .../ref/x86/linux/simple-atomic/config.ini    |    4 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   14 +-
 .../ref/x86/linux/simple-atomic/config.ini    |    2 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   14 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +-
 .../70.twolf/ref/x86/linux/o3-timing/simout   |   10 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  867 +++++-----
 .../ref/x86/linux/simple-atomic/config.ini    |    2 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   14 +-
 .../ref/x86/linux/pc-simple-atomic/config.ini |    6 +-
 .../ref/x86/linux/pc-simple-atomic/simout     |   10 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt  |   14 +-
 .../ref/x86/linux/pc-simple-timing/config.ini |    6 +-
 .../ref/x86/linux/pc-simple-timing/simout     |   10 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  |   14 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +-
 .../00.hello/ref/x86/linux/o3-timing/simout   |   10 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  675 ++++----
 .../ref/x86/linux/simple-atomic/config.ini    |    2 +-
 .../ref/x86/linux/simple-atomic/simout        |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   12 +-
 .../x86/linux/simple-timing-ruby/config.ini   |    2 +-
 .../x86/linux/simple-timing-ruby/ruby.stats   |   30 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |    8 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |   14 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   12 +-
 69 files changed, 3224 insertions(+), 3175 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index f04a1d212..1120c294b 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -1263,7 +1263,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1283,7 +1283,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index e02484e67..807344aef 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 16:05:33
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5169499540500 because m5_exit instruction encountered
+Exiting @ tick 5157514159500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index f1c4ffb88..6732f4df4 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,151 +1,151 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.169500                       # Number of seconds simulated
-sim_ticks                                5169499540500                       # Number of ticks simulated
-final_tick                               5169499540500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.157514                       # Number of seconds simulated
+sim_ticks                                5157514159500                       # Number of ticks simulated
+final_tick                               5157514159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77808                       # Simulator instruction rate (inst/s)
-host_op_rate                                   153328                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              943017240                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 366644                       # Number of bytes of host memory used
-host_seconds                                  5481.87                       # Real time elapsed on the host
-sim_insts                                   426530860                       # Number of instructions simulated
-sim_ops                                     840523890                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    15909184                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1237824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12067392                       # Number of bytes written to this memory
-system.physmem.num_reads                       248581                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      188553                       # Number of write requests responded to by this memory
+host_inst_rate                                  88188                       # Simulator instruction rate (inst/s)
+host_op_rate                                   173786                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1066411603                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 415716                       # Number of bytes of host memory used
+host_seconds                                  4836.33                       # Real time elapsed on the host
+sim_insts                                   426506235                       # Number of instructions simulated
+sim_ops                                     840483958                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read                    15959488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1257664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 12050112                       # Number of bytes written to this memory
+system.physmem.num_reads                       249367                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      188283                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3077510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    239448                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2334344                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5411854                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        167476                       # number of replacements
-system.l2c.tagsinuse                     37831.311454                       # Cycle average of tags in use
-system.l2c.total_refs                         3834095                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        201653                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         19.013330                       # Average number of references to valid blocks.
+system.physmem.bw_read                        3094415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    243851                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2336419                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5430833                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        167142                       # number of replacements
+system.l2c.tagsinuse                     37816.689690                       # Cycle average of tags in use
+system.l2c.total_refs                         3843284                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        202399                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         18.988651                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        26693.996125                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       11.281842                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.035682                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           2446.646461                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           8679.351345                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.407318                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000172                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        26702.073389                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        8.025761                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.043125                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           2426.285000                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           8680.262415                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.407441                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000122                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000001                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.037333                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.132436                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.577260                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        109979                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          9264                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst             1065061                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1335148                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2519452                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1598542                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1598542                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              324                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 324                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            151430                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               151430                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         109979                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           9264                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst              1065061                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1486578                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2670882                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        109979                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          9264                       # number of overall hits
-system.l2c.overall_hits::cpu.inst             1065061                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1486578                       # number of overall hits
-system.l2c.overall_hits::total                2670882                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker          104                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker           11                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             19342                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             45291                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                64748                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2653                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2653                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          141019                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             141019                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker          104                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker           11                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              19342                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             186310                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                205767                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker          104                       # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker           11                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             19342                       # number of overall misses
-system.l2c.overall_misses::cpu.data            186310                       # number of overall misses
-system.l2c.overall_misses::total               205767                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      5428000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker       573500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst   1010710500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   2380797000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     3397509000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     37026000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     37026000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   7343771000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7343771000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      5428000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker       573500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst   1010710500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   9724568000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     10741280000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      5428000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker       573500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst   1010710500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   9724568000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    10741280000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       110083                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         9275                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst         1084403                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1380439                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2584200                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1598542                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1598542                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2977                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2977                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        292449                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292449                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       110083                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         9275                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst          1084403                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1672888                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2876649                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       110083                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         9275                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1084403                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1672888                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2876649                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000945                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001186                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.017837                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.032809                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.891166                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.482200                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000945                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.001186                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.017837                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.111370                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000945                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.001186                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.017837                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.111370                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52136.363636                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52254.704788                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52566.668875                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13956.275914                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52076.464874                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 52136.363636                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52254.704788                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52195.630938                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 52136.363636                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52254.704788                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52195.630938                       # average overall miss latency
+system.l2c.occ_percent::cpu.inst             0.037022                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.132450                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.577037                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        109565                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          8804                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1063948                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1334758                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2517075                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1600724                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1600724                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              336                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 336                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            151728                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               151728                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         109565                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           8804                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1063948                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1486486                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2668803                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        109565                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          8804                       # number of overall hits
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+system.l2c.overall_hits::cpu.data             1486486                       # number of overall hits
+system.l2c.overall_hits::total                2668803                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker          105                       # number of ReadReq misses
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+system.l2c.ReadReq_misses::total                65434                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2521                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2521                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          141129                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             141129                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker          105                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total                206563                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker          105                       # number of overall misses
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+system.l2c.overall_misses::total               206563                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      5480500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       886000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst   1027000000                       # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu.data     39054500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     39054500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7349617000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7349617000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      5480500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       886000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst   1027000000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   9749489000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     10782855500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      5480500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       886000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst   1027000000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   9749489000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    10782855500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       109670                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         8821                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1083600                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1380418                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2582509                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1600724                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1600724                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2857                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2857                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        292857                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292857                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       109670                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         8821                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1083600                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1673275                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2875366                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       109670                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         8821                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu.data         1673275                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2875366                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000957                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001927                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.018136                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.033077                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.882394                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.481904                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000957                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001927                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.018136                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.111631                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000957                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001927                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.018136                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.111631                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52195.198861                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52195.198861                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -154,8 +154,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              141885                       # number of writebacks
-system.l2c.writebacks::total                   141885                       # number of writebacks
+system.l2c.writebacks::writebacks              141616                       # number of writebacks
+system.l2c.writebacks::total                   141616                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
@@ -165,157 +165,157 @@ system.l2c.demand_mshr_hits::total                  2                       # nu
 system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          104                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker           11                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        19341                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        45290                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           64746                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2653                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2653                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       141019                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        141019                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker          104                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker           11                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         19341                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        186309                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           205765                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker          104                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker           11                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total          205765                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      4167500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       440000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    774472500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1827120500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2606200500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    106465000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    106465000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5642238000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5642238000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      4167500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker       440000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    774472500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   7469358500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   8248438500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      4167500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker       440000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    774472500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   7469358500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8248438500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59975752000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59975752000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1229777500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1229777500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  61205529500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  61205529500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000945                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001186                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017836                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.032808                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.891166                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.482200                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000945                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001186                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.017836                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.111370                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000945                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001186                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.017836                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.111370                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          105                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::cpu.data        45659                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           65432                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2521                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2521                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       141129                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        141129                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker          105                       # number of demand (read+write) MSHR misses
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+system.l2c.overall_mshr_misses::total          206561                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      4210000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       680000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    786943000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1841762000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2633595000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    101204500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    101204500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5646584500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5646584500                       # number of ReadExReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       680000                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu.data   7488346500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8280179500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      4210000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       680000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    786943000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   7488346500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8280179500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59975402500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59975402500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1229367500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1229367500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  61204770000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  61204770000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000957                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.033076                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.882394                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.481904                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000957                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.111630                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000957                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.111630                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40043.043276                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40342.691543                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40130.041462                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.480857                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40043.043276                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40091.238212                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40043.043276                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40091.238212                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47577                       # number of replacements
-system.iocache.tagsinuse                     0.202876                       # Cycle average of tags in use
+system.iocache.replacements                     47578                       # number of replacements
+system.iocache.tagsinuse                     0.166155                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47593                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47594                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4996368196000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.202876                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.012680                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.012680                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
+system.iocache.warmup_cycle              4996370640000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.166155                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.010385                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.010385                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          913                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              913                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47631                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47631                       # number of overall misses
-system.iocache.overall_misses::total            47631                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    114136932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    114136932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6374051160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6374051160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   6488188092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   6488188092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   6488188092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   6488188092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47633                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47633                       # number of overall misses
+system.iocache.overall_misses::total            47633                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    114379932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    114379932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6373400160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6373400160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   6487780092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   6487780092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   6487780092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   6487780092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          913                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            913                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47631                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47631                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47631                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47631                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47633                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47633                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47633                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47633                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125287.521405                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136430.889555                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136217.759274                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136217.759274                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      68852524                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs      69025534                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11251                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                11269                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6119.680384                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6125.258142                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46668                       # number of writebacks
-system.iocache.writebacks::total                46668                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          911                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          911                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          913                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          913                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47631                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47631                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47631                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66741982                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     66741982                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3944293874                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3944293874                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4011035856                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4011035856                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4011035856                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4011035856                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47633                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47633                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47633                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66880982                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     66880982                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3943643878                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3943643878                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4010524860                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4010524860                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4010524860                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4010524860                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73262.329308                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84424.098330                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84210.616111                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84210.616111                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -329,141 +329,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        461361546                       # number of cpu cycles simulated
+system.cpu.numCycles                        461333918                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 90046229                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           90046229                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1176099                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              84310101                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 81718791                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 90003796                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           90003796                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1173183                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              84315614                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 81694619                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29608637                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      447015807                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    90046229                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           81718791                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     169801708                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5302195                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     145260                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles              101860609                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                38090                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         39269                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          431                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9372396                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                523997                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5250                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          305583315                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.878441                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.383859                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29624871                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      446885817                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    90003796                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           81694619                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     169759235                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5280537                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     141697                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98681847                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                37486                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         37869                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          332                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9366803                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                526850                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4968                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          302354351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.908315                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.388599                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                136218016     44.58%     44.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1767126      0.58%     45.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72778652     23.82%     68.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   988391      0.32%     69.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1638096      0.54%     69.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3679779      1.20%     71.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1146175      0.38%     71.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1451143      0.47%     71.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85915937     28.12%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                133032171     44.00%     44.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1767192      0.58%     44.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72774261     24.07%     68.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   988290      0.33%     68.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1636300      0.54%     69.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3666710      1.21%     70.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1141173      0.38%     71.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1450765      0.48%     71.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 85897489     28.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            305583315                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.195175                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.968906                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 34706026                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              97971351                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 163987110                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4829517                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4089311                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              876370840                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   830                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4089311                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 38986696                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                68087703                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       10443345                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 164022583                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              19953677                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              872580437                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  9956                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12941208                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3881940                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           873928862                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1709683510                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1709682778                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               732                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             843141263                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 30787592                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             471317                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         478659                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  46567853                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             18906689                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10452552                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1298619                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1044286                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  865700998                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1721462                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 864366018                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            113102                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25970693                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     36970619                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         205740                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     305583315                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.828577                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.402836                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            302354351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.195095                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.968682                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 34659888                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              94852238                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 163950875                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4820336                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4071014                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              876062076                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   946                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4071014                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 38916721                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                39863124                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       10415671                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 164017891                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              45069930                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              872218550                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  9888                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               34551329                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3873333                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         31844673                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1393807250                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2487747342                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2487746606                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               736                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1347499622                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 46307621                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             471559                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         478592                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  46419855                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             18887370                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10441908                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1295912                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1023550                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  865497785                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1720774                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 864256508                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            112298                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        25797308                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     52868004                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         205226                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     302354351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.858423                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.389400                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            99104201     32.43%     32.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            25415077      8.32%     40.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            14237257      4.66%     45.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             9395044      3.07%     48.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            79117426     25.89%     74.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4854972      1.59%     75.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72798510     23.82%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              530953      0.17%     99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              129875      0.04%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            95961743     31.74%     31.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            22211681      7.35%     39.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            18919578      6.26%     45.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7861063      2.60%     47.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            80643893     26.67%     74.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3287491      1.09%     75.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72804898     24.08%     99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              531965      0.18%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              132039      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       305583315                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       302354351                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  169376      8.03%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1775092     84.15%     92.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                164908      7.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  168781      8.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1775830     84.20%     92.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                164454      7.80%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            297276      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             829460280     95.96%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            295147      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             829365439     95.96%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.00% # Type of FU issued
@@ -492,232 +492,232 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.00% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25161401      2.91%     98.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9447061      1.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25156928      2.91%     98.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9438994      1.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              864366018                       # Type of FU issued
-system.cpu.iq.rate                           1.873511                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2109376                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              864256508                       # Type of FU issued
+system.cpu.iq.rate                           1.873386                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2109065                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.002440                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2036675779                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         893403890                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    853968919                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 282                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                338                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              866177988                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     130                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1585170                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_inst_queue_reads         2033227261                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         893026339                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    853844351                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 314                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                348                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           80                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              866070281                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     145                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1582954                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3604924                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        21755                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11989                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2042240                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3588586                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        21998                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11829                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2035325                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7821681                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2629                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      7821677                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2614                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4089311                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                45428780                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6134519                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           867422460                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            315149                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              18906689                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10452552                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             882877                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                5413459                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12395                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11989                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         702330                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       623988                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1326318                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             862468357                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24736140                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1897660                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4071014                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                26002336                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1398631                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           867218559                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            301512                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              18887370                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10441908                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             882377                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 699130                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12813                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11829                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         701390                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       622436                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1323826                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             862339012                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24725426                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1917495                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     33938822                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86500210                       # Number of branches executed
-system.cpu.iew.exec_stores                    9202682                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.869398                       # Inst execution rate
-system.cpu.iew.wb_sent                      862004512                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     853968991                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 668394030                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1167144528                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     33920026                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 86488789                       # Number of branches executed
+system.cpu.iew.exec_stores                    9194600                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.869230                       # Inst execution rate
+system.cpu.iew.wb_sent                      861878636                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     853844431                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 669889199                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1919045631                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.850976                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.572675                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.850817                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.349074                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      426530860                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        840523890                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        26793490                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1515720                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1180385                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    301509545                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.787719                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.863521                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      426506235                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        840483958                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        26630365                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1515546                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1177301                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    298298866                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.817590                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.864095                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    120813310     40.07%     40.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14395799      4.77%     44.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4294572      1.42%     46.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76662723     25.43%     71.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3914441      1.30%     72.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1779119      0.59%     73.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1107804      0.37%     73.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71983621     23.87%     97.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6558156      2.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    117621447     39.43%     39.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14371375      4.82%     44.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4300832      1.44%     45.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     76665686     25.70%     71.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3908070      1.31%     72.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1784515      0.60%     73.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1116090      0.37%     73.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71984342     24.13%     97.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6546509      2.19%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    301509545                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            426530860                       # Number of instructions committed
-system.cpu.commit.committedOps              840523890                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    298298866                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            426506235                       # Number of instructions committed
+system.cpu.commit.committedOps              840483958                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23712074                       # Number of memory references committed
-system.cpu.commit.loads                      15301762                       # Number of loads committed
-system.cpu.commit.membars                      781561                       # Number of memory barriers committed
-system.cpu.commit.branches                   85507623                       # Number of branches committed
+system.cpu.commit.refs                       23705364                       # Number of memory references committed
+system.cpu.commit.loads                      15298781                       # Number of loads committed
+system.cpu.commit.membars                      781557                       # Number of memory barriers committed
+system.cpu.commit.branches                   85502209                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768350160                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 768310964                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6558156                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6546509                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1162189391                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1738738969                       # The number of ROB writes
-system.cpu.timesIdled                         2883863                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       155778231                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9877634963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   426530860                       # Number of Instructions Simulated
-system.cpu.committedOps                     840523890                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             426530860                       # Number of Instructions Simulated
-system.cpu.cpi                               1.081660                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.081660                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.924505                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.924505                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1404302602                       # number of integer regfile reads
-system.cpu.int_regfile_writes               855269990                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        72                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               281075555                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 403685                       # number of misc regfile writes
-system.cpu.icache.replacements                1083950                       # number of replacements
-system.cpu.icache.tagsinuse                510.027693                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8217570                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1084462                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.577555                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            56617488000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.027693                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996148                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996148                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      8217570                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8217570                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8217570                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8217570                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8217570                       # number of overall hits
-system.cpu.icache.overall_hits::total         8217570                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1154822                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1154822                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1154822                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1154822                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1154822                       # number of overall misses
-system.cpu.icache.overall_misses::total       1154822                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  17227563988                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  17227563988                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  17227563988                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  17227563988                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  17227563988                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  17227563988                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9372392                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9372392                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9372392                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9372392                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9372392                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9372392                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123215                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.123215                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.123215                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14917.938858                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14917.938858                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14917.938858                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2880990                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                   1158787398                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1738314967                       # The number of ROB writes
+system.cpu.timesIdled                         2905540                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       158979567                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9853691832                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   426506235                       # Number of Instructions Simulated
+system.cpu.committedOps                     840483958                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             426506235                       # Number of Instructions Simulated
+system.cpu.cpi                               1.081658                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.081658                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.924507                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.924507                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2163089762                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1362601574                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        80                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               281025584                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 403474                       # number of misc regfile writes
+system.cpu.icache.replacements                1083149                       # number of replacements
+system.cpu.icache.tagsinuse                510.211811                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8213603                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1083661                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.579495                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            56616978000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.211811                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996507                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996507                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      8213603                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8213603                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8213603                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8213603                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8213603                       # number of overall hits
+system.cpu.icache.overall_hits::total         8213603                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1153196                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1153196                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1153196                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1153196                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1153196                       # number of overall misses
+system.cpu.icache.overall_misses::total       1153196                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  17226505491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  17226505491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  17226505491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  17226505491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  17226505491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  17226505491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9366799                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9366799                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9366799                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9366799                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9366799                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9366799                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123115                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.123115                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.123115                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2912492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               292                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               289                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  9866.404110                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1570                       # number of writebacks
 system.cpu.icache.writebacks::total              1570                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69061                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        69061                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        69061                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        69061                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        69061                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        69061                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1085761                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1085761                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1085761                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1085761                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1085761                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1085761                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13090786490                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13090786490                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13090786490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13090786490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13090786490                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13090786490                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115847                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115847                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115847                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.784587                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.784587                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.784587                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68394                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        68394                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        68394                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        68394                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        68394                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        68394                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1084802                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1084802                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1084802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1084802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1084802                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1084802                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13093471492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13093471492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13093471492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13093471492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13093471492                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13093471492                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements        11295                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.030801                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          28582                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs        11307                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.527815                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5144328078000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.030801                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.376925                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.376925                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        28593                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        28593                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements        10825                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.011393                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          27185                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs        10834                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.509230                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5135028893000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.011393                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375712                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.375712                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        27407                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        27407                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        28596                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        28596                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        28596                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        28596                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        12165                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        12165                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        12165                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        12165                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        12165                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        12165                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    154895000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    154895000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    154895000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    154895000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    154895000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    154895000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40758                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        40758                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        27410                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        27410                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        27410                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        27410                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        11687                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        11687                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        11687                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        11687                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        11687                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        11687                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    148214000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    148214000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    148214000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    148214000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    148214000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    148214000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        39094                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        39094                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40761                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        40761                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40761                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        40761                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.298469                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.298447                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.298447                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12732.840115                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12732.840115                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12732.840115                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        39097                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        39097                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        39097                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        39097                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.298946                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.298923                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.298923                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -726,66 +726,66 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1487                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1487                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        12165                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        12165                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        12165                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        12165                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        12165                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        12165                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    117952000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    117952000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    117952000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    117952000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    117952000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    117952000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.298469                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.298447                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.298447                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9696.013152                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9696.013152                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9696.013152                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1456                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1456                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        11687                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        11687                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        11687                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        11687                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        11687                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        11687                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    112719500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    112719500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    112719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    112719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    112719500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    112719500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.298946                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.298923                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.298923                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       117758                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       12.948183                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         134592                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       117774                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.142799                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5108639465000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.948183                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.809261                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.809261                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       134592                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       134592                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       134592                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       134592                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       134592                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       134592                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       118727                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       118727                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       118727                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       118727                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       118727                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       118727                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1650934500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1650934500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1650934500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   1650934500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1650934500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   1650934500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       253319                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       253319                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       253319                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       253319                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       253319                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       253319                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.468686                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.468686                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.468686                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13905.299553                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13905.299553                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13905.299553                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements       116553                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       13.859632                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         135956                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       116568                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.166324                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5108641793000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.859632                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.866227                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.866227                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       135961                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       135961                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       135961                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       135961                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       135961                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       135961                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       117570                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       117570                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       117570                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       117570                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       117570                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       117570                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1642151000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1642151000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1642151000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   1642151000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1642151000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   1642151000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       253531                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       253531                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       253531                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       253531                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       253531                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       253531                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -794,124 +794,124 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        34129                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        34129                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       118727                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       118727                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       118727                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total       118727                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       118727                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total       118727                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1291951000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1291951000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1291951000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1291951000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1291951000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1291951000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.468686                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.468686                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.468686                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        36817                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        36817                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       117570                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       117570                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       117570                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       117570                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       117570                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       117570                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1286519500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1286519500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1286519500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1286519500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1286519500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1286519500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1672937                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997030                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 19038676                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1673449                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.376908                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1673290                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997033                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19026186                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1673802                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.367047                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               34328000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997030                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.997033                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     10951636                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10951636                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8083299                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8083299                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19034935                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19034935                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19034935                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19034935                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2412266                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2412266                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       317673                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       317673                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2729939                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2729939                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2729939                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2729939                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36171443000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36171443000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10559722481                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10559722481                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  46731165481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  46731165481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  46731165481                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  46731165481                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13363902                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13363902                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8400972                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8400972                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21764874                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21764874                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21764874                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21764874                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180506                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037814                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.125429                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.125429                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14994.798666                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33240.856104                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17118.025524                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17118.025524                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     23782481                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data     10943323                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10943323                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8079241                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8079241                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19022564                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19022564                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19022564                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19022564                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2411423                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2411423                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       318003                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       318003                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2729426                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2729426                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2729426                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2729426                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36183001500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36183001500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10564799496                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10564799496                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  46747800996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  46747800996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  46747800996                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  46747800996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13354746                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13354746                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8397244                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8397244                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21751990                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21751990                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21751990                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21751990                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180567                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037870                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.125479                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.125479                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     25105497                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              3499                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              3680                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  6796.936553                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6822.145924                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1561356                       # number of writebacks
-system.cpu.dcache.writebacks::total           1561356                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1030690                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1030690                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22348                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        22348                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1053038                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1053038                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1053038                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1053038                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381576                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1381576                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       295325                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       295325                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1676901                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1676901                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1676901                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1676901                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  18163645000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  18163645000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9344995981                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9344995981                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27508640981                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  27508640981                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27508640981                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27508640981                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208124500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208124500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1393505500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1393505500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86601630000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  86601630000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035154                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077046                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077046                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13147.047285                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31643.091445                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16404.451414                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16404.451414                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1560881                       # number of writebacks
+system.cpu.dcache.writebacks::total           1560881                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1029888                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1029888                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22394                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        22394                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1052282                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1052282                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1052282                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1052282                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381535                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1381535                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       295609                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       295609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1677144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1677144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1677144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1677144                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  18178804500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  18178804500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9348322497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9348322497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27527126997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27527126997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27527126997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27527126997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85207754500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85207754500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1392930500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1392930500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86600685000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  86600685000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103449                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035203                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077103                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077103                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
index f0dc7f01e..6570dc326 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
 ACPI: Unable to load the System Description Tables
 Using local APIC timer interrupts.
-result 7812499
+result 7812497
 Detected 7.812 MHz APIC timer.
 NET: Registered protocol family 16
 PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index f293cbb8e..78474a665 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -995,7 +995,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1015,7 +1015,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 5a285fe00..5cc55eff8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 16:45:52
+Real time: May/21/2012 19:39:45
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1474
-Elapsed_time_in_minutes: 24.5667
-Elapsed_time_in_hours: 0.409444
-Elapsed_time_in_days: 0.0170602
+Elapsed_time_in_seconds: 1285
+Elapsed_time_in_minutes: 21.4167
+Elapsed_time_in_hours: 0.356944
+Elapsed_time_in_days: 0.0148727
 
-Virtual_time_in_seconds: 1451.34
-Virtual_time_in_minutes: 24.189
-Virtual_time_in_hours:   0.40315
-Virtual_time_in_days:    0.0167979
+Virtual_time_in_seconds: 1013.41
+Virtual_time_in_minutes: 16.8902
+Virtual_time_in_hours:   0.281503
+Virtual_time_in_days:    0.0117293
 
 Ruby_current_time: 10609379371
 Ruby_start_time: 0
 Ruby_cycles: 10609379371
 
-mbytes_resident: 266.27
-mbytes_total: 468.445
-resident_ratio: 0.568411
+mbytes_resident: 269.652
+mbytes_total: 517.469
+resident_ratio: 0.521114
 
 ruby_cycles_executed: [ 10609379372 10609379372 ]
 
@@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 1451
+user_time: 1013
 system_time: 0
-page_reclaims: 69308
-page_faults: 15
+page_reclaims: 70791
+page_faults: 113
 swaps: 0
-block_inputs: 14664
-block_outputs: 768
+block_inputs: 0
+block_outputs: 0
 
 Network Stats
 -------------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index 3387e35c8..4bb71c433 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 16:21:06
-gem5 started May  8 2012 16:21:17
-gem5 executing on piton
+gem5 compiled May 21 2012 19:18:11
+gem5 started May 21 2012 19:18:20
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5304689685500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index 2c42d3233..c2f297e1d 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.304690                       # Nu
 sim_ticks                                5304689685500                       # Number of ticks simulated
 final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93103                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190197                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3598037208                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 479692                       # Number of bytes of host memory used
-host_seconds                                  1474.33                       # Real time elapsed on the host
+host_inst_rate                                 106822                       # Simulator instruction rate (inst/s)
+host_op_rate                                   218222                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4128199893                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 529892                       # Number of bytes of host memory used
+host_seconds                                  1284.99                       # Real time elapsed on the host
 sim_insts                                   137264752                       # Number of instructions simulated
 sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1392025556                       # Number of bytes read from this memory
@@ -44,8 +44,8 @@ system.cpu0.num_func_calls                          0                       # nu
 system.cpu0.num_conditional_control_insts     17923925                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                   168469813                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          360430418                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         178581746                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          517963582                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         280483339                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
 system.cpu0.num_mem_refs                     19132508                       # number of memory refs
@@ -68,8 +68,8 @@ system.cpu1.num_func_calls                          0                       # nu
 system.cpu1.num_conditional_control_insts      8197841                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    89110416                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          197924728                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          89969833                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          273178552                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         138760228                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
 system.cpu1.num_mem_refs                     14426742                       # number of memory refs
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index ebc83b22f..c9c059053 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -516,7 +516,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index fe3d3cd18..c90f0d12f 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:46
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -40,4 +42,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 637054100000 because target called exit()
+Exiting @ tick 636988382500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 7852ddedb..cda4c39ac 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,157 +1,158 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.637054                       # Number of seconds simulated
-sim_ticks                                637054100000                       # Number of ticks simulated
-final_tick                               637054100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.636988                       # Number of seconds simulated
+sim_ticks                                636988382500                       # Number of ticks simulated
+final_tick                               636988382500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56200                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103552                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40683578                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226404                       # Number of bytes of host memory used
-host_seconds                                 15658.75                       # Real time elapsed on the host
+host_inst_rate                                  47331                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87209                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34259348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276376                       # Number of bytes of host memory used
+host_seconds                                 18593.13                       # Real time elapsed on the host
 sim_insts                                   880025312                       # Number of instructions simulated
 sim_ops                                    1621493982                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                     5835840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  58688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  3733184                       # Number of bytes written to this memory
-system.physmem.num_reads                        91185                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       58331                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                     5834048                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  59200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3731712                       # Number of bytes written to this memory
+system.physmem.num_reads                        91157                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58308                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        9160666                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                     92124                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5860074                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      15020740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                        9158798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     92937                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5858367                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      15017166                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1274108201                       # number of cpu cycles simulated
+system.cpu.numCycles                       1273976766                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                154805091                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          154805091                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           26670333                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              76796607                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 76433583                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                154678064                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          154678064                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           26667110                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              77406078                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 77035710                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          180707581                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1491843077                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   154805091                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           76433583                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     402290589                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                93779674                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              624095429                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  186                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1350                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 186629859                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               9332096                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1274045731                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.001845                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.237422                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          180711057                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1490230522                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   154678064                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           77035710                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     402278451                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                93695646                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              624053491                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1298                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 186830267                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               9529255                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1273914012                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.999814                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.235188                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                878972627     68.99%     68.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24230578      1.90%     70.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 15474142      1.21%     72.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 17847771      1.40%     73.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26734269      2.10%     75.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18266815      1.43%     77.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 28459666      2.23%     79.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 39787641      3.12%     82.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                224272222     17.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                878853214     68.99%     68.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 24303546      1.91%     70.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15677834      1.23%     72.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 17928928      1.41%     73.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26735770      2.10%     75.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18262172      1.43%     77.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 28765750      2.26%     79.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 39797773      3.12%     82.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                223589025     17.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1274045731                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.121501                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.170892                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                300115536                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             537090427                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 281718880                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              88170292                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               66950596                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2369584116                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               66950596                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                352574967                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               124103280                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2679                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 302559797                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             427854412                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2273931919                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   193                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              293394028                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             103133099                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2267658104                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5579907383                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5579899199                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              8184                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                649663454                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                100                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            100                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 745849512                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            546580267                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           222259773                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         352635383                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        146994929                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2027928806                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 590                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1785553597                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            119193                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       406267408                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    856006289                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            540                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1274045731                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.401483                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.311552                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1273914012                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.121414                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.169747                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                300082895                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             537078967                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 281798821                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              88083788                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               66869541                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2368899404                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               66869541                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                352603459                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               124071504                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2838                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 302490800                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             427875870                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2273771459                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   200                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              293326885                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             103161675                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              640                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3463149697                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            7120628186                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       7120621006                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7180                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            2493860970                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                969288727                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                110                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            110                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 746079760                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            546341437                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222247757                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         352469730                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        147023702                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2027529381                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 546                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1785574895                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            118982                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       405869160                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1051620727                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            496                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1273914012                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.401645                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.311838                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           347008054     27.24%     27.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           447518543     35.13%     62.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           243291159     19.10%     81.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           151236902     11.87%     93.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            40950901      3.21%     96.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            32374953      2.54%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9944821      0.78%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1368449      0.11%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              351949      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           347011243     27.24%     27.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           447440187     35.12%     62.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           243114047     19.08%     81.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151317630     11.88%     93.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            40944695      3.21%     96.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            32410749      2.54%     99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9957171      0.78%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1368147      0.11%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              350143      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1274045731                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1273914012                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  236653      9.21%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2158500     84.00%     93.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                174415      6.79%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  237387      9.29%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2138623     83.73%     93.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                178205      6.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          46809774      2.62%      2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1066762754     59.74%     62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          46809715      2.62%      2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1066790690     59.74%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.37% # Type of FU issued
@@ -180,86 +181,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.37% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            479507335     26.85%     89.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192473734     10.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            479501542     26.85%     89.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192472948     10.78%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1785553597                       # Type of FU issued
-system.cpu.iq.rate                           1.401414                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2569568                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001439                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4847841100                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2434377268                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1726804996                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 586                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2320                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           60                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1741313206                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     185                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        208932159                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1785574895                       # Type of FU issued
+system.cpu.iq.rate                           1.401576                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2554215                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001430                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4847736227                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2433580235                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1726806271                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 772                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2168                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           84                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1741319146                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     249                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        208956586                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    127538142                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        36788                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       189688                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     34073716                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    127299312                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        36681                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       190307                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     34061700                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2016                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads         1845                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               66950596                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  381980                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 88146                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2027929396                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          63814072                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             546580267                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            222259773                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 94                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  48025                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   420                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         189688                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2136326                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     24658477                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             26794803                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1767571508                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             473890078                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          17982089                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               66869541                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  356934                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 88692                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2027529927                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          63849570                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             546341437                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222247757                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                103                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  48888                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   421                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         190307                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2139656                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     24653796                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             26793452                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1767588629                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             473898164                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          17986266                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    665732549                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                109682584                       # Number of branches executed
-system.cpu.iew.exec_stores                  191842471                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.387301                       # Inst execution rate
-system.cpu.iew.wb_sent                     1728142176                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1726805056                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1262100818                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1868205499                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    665742013                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                109684623                       # Number of branches executed
+system.cpu.iew.exec_stores                  191843849                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.387458                       # Inst execution rate
+system.cpu.iew.wb_sent                     1728148485                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1726806355                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1262041827                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2984894242                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.355305                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.675569                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.355446                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.422810                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      880025312                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1621493982                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       406439731                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       406040141                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          26670511                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1207095135                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.343303                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.660532                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          26667277                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1207044471                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.343359                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.660546                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    437349851     36.23%     36.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    432546759     35.83%     72.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     93488393      7.74%     79.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    134921626     11.18%     90.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     35737028      2.96%     93.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     23235805      1.92%     95.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     25789335      2.14%     98.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8868292      0.73%     98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15158046      1.26%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    437250010     36.22%     36.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    432641487     35.84%     72.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     93464877      7.74%     79.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    134893392     11.18%     90.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     35716518      2.96%     93.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23306370      1.93%     95.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     25727632      2.13%     98.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8874629      0.74%     98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15169556      1.26%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1207095135                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1207044471                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            880025312                       # Number of instructions committed
 system.cpu.commit.committedOps             1621493982                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -270,62 +271,62 @@ system.cpu.commit.branches                  107161579                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15158046                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15169556                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3219870802                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4122835024                       # The number of ROB writes
-system.cpu.timesIdled                            1341                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           62470                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3219409038                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4121954747                       # The number of ROB writes
+system.cpu.timesIdled                            1354                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           62754                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   880025312                       # Number of Instructions Simulated
 system.cpu.committedOps                    1621493982                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             880025312                       # Number of Instructions Simulated
-system.cpu.cpi                               1.447809                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.447809                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.690699                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.690699                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3282350370                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1699874197                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               911417902                       # number of misc regfile reads
-system.cpu.icache.replacements                     15                       # number of replacements
-system.cpu.icache.tagsinuse                828.919506                       # Cycle average of tags in use
-system.cpu.icache.total_refs                186628505                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    920                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               202857.070652                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.447659                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.447659                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.690770                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.690770                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4473469244                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2589680881                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        84                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               911429698                       # number of misc regfile reads
+system.cpu.icache.replacements                     22                       # number of replacements
+system.cpu.icache.tagsinuse                827.099302                       # Cycle average of tags in use
+system.cpu.icache.total_refs                186828876                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    928                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               201324.219828                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     828.919506                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.404746                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.404746                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    186628507                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       186628507                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     186628507                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        186628507                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    186628507                       # number of overall hits
-system.cpu.icache.overall_hits::total       186628507                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1352                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1352                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1352                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1352                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1352                       # number of overall misses
-system.cpu.icache.overall_misses::total          1352                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     45933500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     45933500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     45933500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     45933500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     45933500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     45933500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    186629859                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    186629859                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    186629859                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    186629859                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    186629859                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    186629859                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     827.099302                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.403857                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.403857                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    186828882                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       186828882                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     186828882                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        186828882                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    186828882                       # number of overall hits
+system.cpu.icache.overall_hits::total       186828882                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1385                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1385                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1385                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1385                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1385                       # number of overall misses
+system.cpu.icache.overall_misses::total          1385                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     46636000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     46636000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     46636000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     46636000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     46636000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     46636000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    186830267                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    186830267                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    186830267                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    186830267                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    186830267                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    186830267                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33974.482249                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33974.482249                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33974.482249                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -334,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          428                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          428                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          428                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          428                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          428                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          428                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          924                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          924                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          924                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          924                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          924                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          924                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32509500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     32509500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32509500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     32509500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32509500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     32509500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          450                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          450                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          450                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          450                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          450                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          450                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          935                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          935                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          935                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          935                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          935                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          935                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32805000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     32805000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32805000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     32805000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32805000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     32805000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35183.441558                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35183.441558                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35183.441558                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 445461                       # number of replacements
-system.cpu.dcache.tagsinuse               4093.514188                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                452687573                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 449557                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1006.963684                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              723787000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4093.514188                       # Average occupied blocks per requestor
+system.cpu.dcache.replacements                 445407                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.514636                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                452671406                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 449503                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1007.048687                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              723816000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.514636                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999393                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999393                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    264747763                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       264747763                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    187939802                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      187939802                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     452687565                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        452687565                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    452687565                       # number of overall hits
-system.cpu.dcache.overall_hits::total       452687565                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       206758                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        206758                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       246255                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       246255                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       453013                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         453013                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       453013                       # number of overall misses
-system.cpu.dcache.overall_misses::total        453013                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2151695000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2151695000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3209973000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3209973000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   5361668000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   5361668000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   5361668000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   5361668000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    264954521                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    264954521                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::cpu.data    264731564                       # number of ReadReq hits
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+system.cpu.dcache.overall_hits::total       452671394                       # number of overall hits
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+system.cpu.dcache.demand_misses::total         452971                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       452971                       # number of overall misses
+system.cpu.dcache.overall_misses::total        452971                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2148724000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2148724000                       # number of ReadReq miss cycles
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+system.cpu.dcache.ReadReq_accesses::cpu.data    264938308                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    264938308                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    453140578                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    453140578                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    453140578                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    453140578                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    453124365                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    453124365                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    453124365                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    453124365                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000780                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001309                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001308                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.001000                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.001000                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10406.828273                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13035.158677                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11835.572048                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11835.572048                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -416,120 +417,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       400737                       # number of writebacks
-system.cpu.dcache.writebacks::total            400737                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3424                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         3424                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           26                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           26                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         3450                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         3450                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         3450                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         3450                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203334                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       203334                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246229                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       246229                       # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total       449563                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       449563                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       449563                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1514738500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1514738500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2470762000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2470762000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3985500500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   3985500500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3985500500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   3985500500                       # number of overall MSHR miss cycles
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+system.cpu.dcache.writebacks::total            400713                       # number of writebacks
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+system.cpu.dcache.overall_mshr_miss_latency::total   3996172000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000767                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001308                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7449.509182                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10034.406995                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8865.276947                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8865.276947                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7432.029905                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8890.022958                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8890.022958                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 72913                       # number of replacements
-system.cpu.l2cache.tagsinuse             17778.272536                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  433720                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 88532                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  4.899020                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 72883                       # number of replacements
+system.cpu.l2cache.tagsinuse             17779.692577                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  433456                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 88505                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.897531                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15879.906924                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     60.867967                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1837.497645                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.484616                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001858                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.056076                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.542550                       # Average percentage of cache occupancy
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 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       171422                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         171425                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       400737                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       400737                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187869                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187869                       # number of ReadExReq hits
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 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       359291                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       359291                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         359294                       # number of overall hits
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-system.cpu.l2cache.ReadReq_accesses::total       204244                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       400737                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       400737                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            4                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            4                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246235                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246235                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          920                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       449559                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       450479                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          920                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       449559                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       450479                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996739                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.156902                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.237034                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996739                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.200792                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996739                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.200792                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.080698                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34270.343552                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34232.901004                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.080698                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34246.133735                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.080698                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34246.133735                       # average overall miss latency
+system.cpu.l2cache.overall_hits::cpu.data       359273                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         359276                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          925                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31911                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32836                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        58321                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        58321                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          925                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        90232                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         91157                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          925                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        90232                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        91157                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31707500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1094294500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1126002000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1998540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1998540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     31707500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3092835000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3124542500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     31707500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3092835000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3124542500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          928                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       203302                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       204230                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       400713                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       400713                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            7                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            7                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246203                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246203                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          928                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       449505                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       450433                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          928                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       449505                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       450433                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996767                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.156964                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.236882                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200736                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200736                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -538,44 +539,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        58331                       # number of writebacks
-system.cpu.l2cache.writebacks::total            58331                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          917                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31902                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        32819                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58366                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        58366                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          917                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        90268                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        91185                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          917                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        90268                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        91185                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     28488000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    989063500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1017551500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1809374000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1809374000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28488000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2798437500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   2826925500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28488000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2798437500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   2826925500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996739                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.156902                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.237034                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996739                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200792                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996739                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200792                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31066.521265                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.181619                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.479731                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31066.521265                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.434617                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31066.521265                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.434617                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        58308                       # number of writebacks
+system.cpu.l2cache.writebacks::total            58308                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          925                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31911                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32836                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58321                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        58321                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          925                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        90232                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        91157                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          925                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        90232                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        91157                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     28735500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    989353500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1018089000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1807989500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1807989500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28735500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2797343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2826078500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28735500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2797343000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2826078500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996767                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.156964                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.236882                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200736                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996767                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200736                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 67df96739..d68307ad3 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -103,7 +103,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
index 7e883d441..dc2715495 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:47
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:03:31
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 8fa6b9f22..8ef9855df 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.963993                       # Nu
 sim_ticks                                963992704000                       # Number of ticks simulated
 final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 616329                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1135620                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              675136354                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215452                       # Number of bytes of host memory used
-host_seconds                                  1427.85                       # Real time elapsed on the host
+host_inst_rate                                 650115                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1197871                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              712145069                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265536                       # Number of bytes of host memory used
+host_seconds                                  1353.65                       # Real time elapsed on the host
 sim_insts                                   880025313                       # Number of instructions simulated
 sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 11334586825                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1621354493                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          3953866002                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          5129484084                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2493860970                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     607228182                       # number of memory refs
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index 2b913aed8..041723c3f 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -185,7 +185,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index f955c1c10..0fb9c1553 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:52:52
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:59
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index ef0537a2c..a3fe13db1 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.803259                       # Nu
 sim_ticks                                1803258587000                       # Number of ticks simulated
 final_tick                               1803258587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 328587                       # Simulator instruction rate (inst/s)
-host_op_rate                                   605440                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              673307954                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224396                       # Number of bytes of host memory used
-host_seconds                                  2678.21                       # Real time elapsed on the host
+host_inst_rate                                 373686                       # Simulator instruction rate (inst/s)
+host_op_rate                                   688537                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              765720435                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274452                       # Number of bytes of host memory used
+host_seconds                                  2354.98                       # Real time elapsed on the host
 sim_insts                                   880025313                       # Number of instructions simulated
 sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5725952                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1621354493                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          3953866002                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          5129484084                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2493860970                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     607228182                       # number of memory refs
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index fdde370ab..cb0a90f11 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -516,9 +516,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index b77e7822e..d6b0619bd 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:53:18
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:10:14
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -21,8 +23,7 @@ new implicit arcs          : 23867
 active arcs                : 25772
 simplex iterations         : 2663
 flow value                 : 3080014995
+info: Increasing stack size by one page.
 checksum                   : 68389
 optimal
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-Exiting @ tick 67367177000 because target called exit()
+Exiting @ tick 67388458000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index ce63fccea..a58d7758c 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,160 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.067367                       # Number of seconds simulated
-sim_ticks                                 67367177000                       # Number of ticks simulated
-final_tick                                67367177000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.067388                       # Number of seconds simulated
+sim_ticks                                 67388458000                       # Number of ticks simulated
+final_tick                                67388458000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46452                       # Simulator instruction rate (inst/s)
-host_op_rate                                    81794                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               19807267                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 361860                       # Number of bytes of host memory used
-host_seconds                                  3401.13                       # Real time elapsed on the host
+host_inst_rate                                  49866                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87805                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               21269638                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411868                       # Number of bytes of host memory used
+host_seconds                                  3168.29                       # Real time elapsed on the host
 sim_insts                                   157988582                       # Number of instructions simulated
 sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                     3905024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  69056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                   895552                       # Number of bytes written to this memory
-system.physmem.num_reads                        61016                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       13993                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                     3907520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  69248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                   897536                       # Number of bytes written to this memory
+system.physmem.num_reads                        61055                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       14024                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       57966270                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1025069                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      13293595                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      71259866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                       57985004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1027594                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      13318839                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      71303843                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        134734355                       # number of cpu cycles simulated
+system.cpu.numCycles                        134776917                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 36117705                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           36117705                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1086223                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              25647744                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 25539011                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 36128556                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           36128556                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1088012                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              25661198                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 25550813                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           27986454                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      196428178                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36117705                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           25539011                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59419496                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8404854                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               39237097                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   32                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           161                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  27269445                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                142050                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          133931620                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.578005                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.358197                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27997413                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      196488492                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36128556                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           25550813                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59432634                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8416233                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               39238726                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  27278821                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                142192                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          133966907                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.578141                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.358289                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 77253594     57.68%     57.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2167416      1.62%     59.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2996676      2.24%     61.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4105343      3.07%     64.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8023701      5.99%     70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5042154      3.76%     74.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2892095      2.16%     76.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1463696      1.09%     77.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 29986945     22.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 77274639     57.68%     57.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2166516      1.62%     59.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2997281      2.24%     61.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4102912      3.06%     64.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8026102      5.99%     70.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5043006      3.76%     74.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2893464      2.16%     76.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1468336      1.10%     77.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29994651     22.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            133931620                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.268066                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.457892                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40456608                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              30121503                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46487725                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9577404                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                7288380                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              341192383                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                7288380                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45850157                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5075267                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9166                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  50344983                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25363667                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              337332641                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    37                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  24553                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              23217040                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           301814702                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             829797290                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        829794179                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3111                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 53470510                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                483                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            475                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  56181617                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            108142373                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37171875                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          46300098                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          7898843                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  331653497                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2738                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 311383007                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            186497                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        53202508                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     70962751                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2292                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     133931620                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.324940                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.724540                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            133966907                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.268062                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.457879                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40465112                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              30125694                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46506148                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9571987                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7297966                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              341297669                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7297966                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45865108                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5065508                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9277                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  50351191                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              25377857                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              337406380                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    13                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   3712                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              23187560                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            79157                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           414755881                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1009935088                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1009932388                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2700                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             341010940                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 73744941                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            474                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  56192967                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            108162580                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37173372                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          46311356                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          7909478                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  331723465                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2616                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 311412241                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            185399                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53269773                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     92543278                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2170                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     133966907                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.324546                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.724461                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            27909124     20.84%     20.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17260254     12.89%     33.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25571257     19.09%     52.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            31151034     23.26%     76.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            17658757     13.18%     89.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             9043417      6.75%     96.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3762327      2.81%     98.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1502538      1.12%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               72912      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            27936582     20.85%     20.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17254518     12.88%     33.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25564521     19.08%     52.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            31166509     23.26%     76.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            17676068     13.19%     89.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             9033591      6.74%     96.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3761456      2.81%     98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1501105      1.12%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               72557      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       133931620                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       133966907                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   23628      1.12%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1962682     92.75%     93.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                129707      6.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   23354      1.11%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1960413     92.78%     93.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                129107      6.11%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             31371      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             177172854     56.90%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             177196652     56.90%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 149      0.00%     56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 116      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.91% # Type of FU issued
@@ -180,86 +181,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.91% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.91% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             99705652     32.02%     88.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34472981     11.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99714062     32.02%     88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34470040     11.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              311383007                       # Type of FU issued
-system.cpu.iq.rate                           2.311088                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2116017                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006796                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          758999086                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         384888890                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    308243683                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                1062                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1674                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          367                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              313467157                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     496                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         52573681                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              311412241                       # Type of FU issued
+system.cpu.iq.rate                           2.310575                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2112874                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006785                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          759088710                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         385026224                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    308270248                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 952                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1427                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          314                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              313493303                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     441                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         52569930                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     17362985                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        99732                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        32451                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      5732124                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17383192                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        98849                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        32443                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5733621                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3310                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3854                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3316                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3845                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                7288380                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  913145                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 89980                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           331656235                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             45880                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             108142373                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37171875                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                7297966                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  891871                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 89086                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           331726081                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             45756                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             108162580                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37173372                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                476                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1173                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 43472                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          32451                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         613492                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       579011                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1192503                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             309419383                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              99171010                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1963624                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                    224                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 43423                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          32443                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         615219                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       578970                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1194189                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             309448819                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              99181332                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1963422                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    133254790                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31526578                       # Number of branches executed
-system.cpu.iew.exec_stores                   34083780                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.296514                       # Inst execution rate
-system.cpu.iew.wb_sent                      308790761                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     308244050                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 227493444                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 314310835                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    133262430                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31528913                       # Number of branches executed
+system.cpu.iew.exec_stores                   34081098                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.296008                       # Inst execution rate
+system.cpu.iew.wb_sent                      308818207                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     308270562                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227514859                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 467066838                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.287791                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.723785                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.287265                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.487114                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        53467881                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        53537768                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1086244                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    126643240                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.196663                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.674492                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1088027                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    126668941                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.196217                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.674380                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     46336828     36.59%     36.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24193827     19.10%     55.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     16853923     13.31%     69.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12623187      9.97%     78.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3354078      2.65%     81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3557907      2.81%     84.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2707686      2.14%     86.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1157110      0.91%     87.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15858694     12.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     46359304     36.60%     36.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24201081     19.11%     55.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     16849760     13.30%     69.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12619079      9.96%     78.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3360251      2.65%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3556898      2.81%     84.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2707142      2.14%     86.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1157073      0.91%     87.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15858353     12.52%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    126643240                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    126668941                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
 system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -270,63 +271,63 @@ system.cpu.commit.branches                   29309710                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15858694                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15858353                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    442444946                       # The number of ROB reads
-system.cpu.rob.rob_writes                   670617818                       # The number of ROB writes
-system.cpu.timesIdled                           23939                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          802735                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    442540875                       # The number of ROB reads
+system.cpu.rob.rob_writes                   670767297                       # The number of ROB writes
+system.cpu.timesIdled                           23993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          810010                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
-system.cpu.cpi                               0.852811                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.852811                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.172593                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.172593                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                549500021                       # number of integer regfile reads
-system.cpu.int_regfile_writes               275642637                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       429                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      242                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               197910962                       # number of misc regfile reads
-system.cpu.icache.replacements                    103                       # number of replacements
-system.cpu.icache.tagsinuse                848.450455                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 27268036                       # Total number of references to valid blocks.
+system.cpu.cpi                               0.853080                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.853080                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.172223                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.172223                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                705322543                       # number of integer regfile reads
+system.cpu.int_regfile_writes               373244258                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       361                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      193                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               197929880                       # number of misc regfile reads
+system.cpu.icache.replacements                     97                       # number of replacements
+system.cpu.icache.tagsinuse                846.508998                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27277404                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   1093                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               24947.882891                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               24956.453797                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     848.450455                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.414282                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.414282                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     27268036                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27268036                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27268036                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27268036                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27268036                       # number of overall hits
-system.cpu.icache.overall_hits::total        27268036                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1409                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1409                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1409                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1409                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1409                       # number of overall misses
-system.cpu.icache.overall_misses::total          1409                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     50108000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     50108000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     50108000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     50108000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     50108000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     50108000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27269445                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27269445                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27269445                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27269445                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27269445                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27269445                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     846.508998                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.413334                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.413334                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     27277408                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27277408                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27277408                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27277408                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27277408                       # number of overall hits
+system.cpu.icache.overall_hits::total        27277408                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1413                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1413                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1413                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1413                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1413                       # number of overall misses
+system.cpu.icache.overall_misses::total          1413                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     50201500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     50201500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     50201500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     50201500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     50201500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     50201500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27278821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27278821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27278821                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27278821                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27278821                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27278821                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35562.810504                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35562.810504                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35562.810504                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -341,74 +342,74 @@ system.cpu.icache.demand_mshr_hits::cpu.inst          315
 system.cpu.icache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          315                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          315                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1094                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1094                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1094                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1094                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1094                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1094                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38230000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     38230000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38230000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     38230000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38230000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     38230000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1098                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1098                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1098                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1098                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1098                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1098                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38330500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     38330500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38330500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     38330500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38330500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     38330500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34945.155393                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34945.155393                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34945.155393                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2072116                       # number of replacements
-system.cpu.dcache.tagsinuse               4072.716490                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 75611002                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2076212                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  36.417766                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            22583642000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4072.716490                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994316                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994316                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     44257159                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        44257159                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31353834                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31353834                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      75610993                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         75610993                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     75610993                       # number of overall hits
-system.cpu.dcache.overall_hits::total        75610993                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2289224                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2289224                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        85917                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        85917                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2375141                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2375141                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2375141                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2375141                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13801326000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13801326000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1502330294                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1502330294                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  15303656294                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  15303656294                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  15303656294                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  15303656294                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46546383                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46546383                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072128                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.706371                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 75623437                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076224                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  36.423544                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            22601159000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.706371                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994313                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994313                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     44269678                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        44269678                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31353743                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31353743                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      75623421                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         75623421                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     75623421                       # number of overall hits
+system.cpu.dcache.overall_hits::total        75623421                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2291019                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2291019                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        86008                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        86008                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2377027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2377027                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2377027                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2377027                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13818885500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13818885500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1502429791                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1502429791                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15321315291                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15321315291                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15321315291                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15321315291                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46560697                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46560697                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     77986134                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     77986134                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     77986134                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     77986134                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049182                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002733                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.030456                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.030456                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6028.822867                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17485.832769                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  6443.262229                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  6443.262229                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     78000448                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     78000448                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     78000448                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     78000448                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049205                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002736                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.030475                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.030475                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6031.763813                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  6445.578990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  6445.578990                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -417,121 +418,123 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1879081                       # number of writebacks
-system.cpu.dcache.writebacks::total           1879081                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295092                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295092                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3834                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         3834                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       298926                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       298926                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       298926                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       298926                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994132                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994132                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82083                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82083                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076215                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076215                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076215                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076215                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5588966000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5588966000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1158785294                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1158785294                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6747751294                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6747751294                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6747751294                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6747751294                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042842                       # mshr miss rate for ReadReq accesses
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 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002611                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026623                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2802.706140                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14117.238576                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3250.025308                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3250.025308                       # average overall mshr miss latency
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2806.348172                       # average ReadReq mshr miss latency
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+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3253.508541                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3253.508541                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 33385                       # number of replacements
-system.cpu.l2cache.tagsinuse             18998.818974                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3761978                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 61393                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 61.276986                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 33429                       # number of replacements
+system.cpu.l2cache.tagsinuse             18994.164700                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3761791                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 61439                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 61.228064                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 12949.193091                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    250.074892                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   5799.550991                       # Average occupied blocks per requestor
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -540,50 +543,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        13993                       # number of writebacks
-system.cpu.l2cache.writebacks::total            13993                       # number of writebacks
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33519500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1858773500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1892293000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.987191                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.015257                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358998                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.987191                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028868                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.987191                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.338276                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31021.546907                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        14024                       # number of writebacks
+system.cpu.l2cache.writebacks::total            14024                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1082                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30455                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        29518                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1082                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        59973                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        61055                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1082                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        59973                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        61055                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     33615000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    944732500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    978347500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    915134000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    915134000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     33615000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1859866500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1893481500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33615000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1859866500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1893481500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.015273                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028886                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.989031                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028886                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.405556                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.338276                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31012.121060                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.338276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31012.121060                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index de9967710..3db1877d2 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -103,9 +103,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 356a4d94b..fce15c036 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:53:55
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 458361cdf..6c9341510 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950072000                       # Number of ticks simulated
 final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 603392                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1062476                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              645256130                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 350676                       # Number of bytes of host memory used
-host_seconds                                   261.83                       # Real time elapsed on the host
+host_inst_rate                                 714486                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1258095                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              764057931                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 400764                       # Number of bytes of host memory used
+host_seconds                                   221.12                       # Real time elapsed on the host
 sim_insts                                   157988583                       # Number of instructions simulated
 sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    278186228                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           834011906                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     122219139                       # number of memory refs
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 6201e2d0e..8da90e4f8 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -185,9 +185,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index e263a1050..704c6b28f 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:54:19
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 763b60bb2..3b408b67c 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.370011                       # Nu
 sim_ticks                                370010840000                       # Number of ticks simulated
 final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 306323                       # Simulator instruction rate (inst/s)
-host_op_rate                                   539385                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              717411215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 359620                       # Number of bytes of host memory used
-host_seconds                                   515.76                       # Real time elapsed on the host
+host_inst_rate                                 298215                       # Simulator instruction rate (inst/s)
+host_op_rate                                   525109                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              698422266                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 409692                       # Number of bytes of host memory used
+host_seconds                                   529.78                       # Real time elapsed on the host
 sim_insts                                   157988583                       # Number of instructions simulated
 sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    278186228                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           834011906                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     122219139                       # number of memory refs
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 1999a5e16..d1e37fed4 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -516,9 +516,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 17ab966f1..b3e00ff1f 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,28 +1,17 @@
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:55:07
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: ***********************info: Increasing stack size by one page.
-***************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-***********
+**************************
  58924 words stored in 3784810 bytes
 
 
@@ -32,6 +21,8 @@ Welcome to the Link Parser -- Version 2.1
 
 Processing sentences in batch mode
 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
 * do you know where John 's 
@@ -75,9 +66,19 @@ Echoing of input sentence turned on.
   the man with whom I play tennis is here 
   there is a dog in the park 
   this is not the man we know and love 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
   we like to eat at restaurants , usually on weekends 
   what did John say he thought you should do 
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 460107924500 because target called exit()
+Exiting @ tick 459937575500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index bb5fef875..5c1bbec0f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,157 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.460108                       # Number of seconds simulated
-sim_ticks                                460107924500                       # Number of ticks simulated
-final_tick                               460107924500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.459938                       # Number of seconds simulated
+sim_ticks                                459937575500                       # Number of ticks simulated
+final_tick                               459937575500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59697                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110386                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               33217787                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263000                       # Number of bytes of host memory used
-host_seconds                                 13851.25                       # Real time elapsed on the host
+host_inst_rate                                  49599                       # Simulator instruction rate (inst/s)
+host_op_rate                                    91715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               27588814                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313336                       # Number of bytes of host memory used
+host_seconds                                 16671.16                       # Real time elapsed on the host
 sim_insts                                   826877144                       # Number of instructions simulated
 sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    37486912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 378624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 26317760                       # Number of bytes written to this memory
-system.physmem.num_reads                       585733                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      411215                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                    37483008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 379264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26316864                       # Number of bytes written to this memory
+system.physmem.num_reads                       585672                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411201                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       81474172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    822903                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      57199102                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     138673273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                       81495859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    824599                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      57218339                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     138714198                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        920215850                       # number of cpu cycles simulated
+system.cpu.numCycles                        919875152                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                225637815                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          225637815                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           14289291                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             160516526                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                155855542                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                225607243                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          225607243                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           14288733                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             160422197                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                155872353                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          191547382                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1262992642                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225637815                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          155855542                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     392021264                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                98465808                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              234027765                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                26184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        270251                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 183405801                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3663632                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          901816172                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.595997                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.389419                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          191636234                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1263077256                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225607243                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155872353                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     392059630                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                98480346                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              233495655                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                26883                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        277282                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 183482871                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3659349                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          901432928                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.597231                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.389695                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                514254997     57.02%     57.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25968939      2.88%     59.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 29098594      3.23%     63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 30321386      3.36%     66.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 19622378      2.18%     68.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 25616419      2.84%     71.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 32613002      3.62%     75.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30831455      3.42%     78.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                193489002     21.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                513839664     57.00%     57.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25974503      2.88%     59.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 29108148      3.23%     63.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 30308604      3.36%     66.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 19639160      2.18%     68.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 25619098      2.84%     71.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32630243      3.62%     75.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 30828862      3.42%     78.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                193484646     21.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            901816172                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.245201                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.372496                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                252794809                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             186036258                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 330006285                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49055494                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               83923326                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2290111824                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               83923326                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                289463344                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                42750657                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14592                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 340217218                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             145447035                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2240140505                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  3227                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               23735126                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             104491412                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2078098051                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5261736827                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5260872310                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            864517                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                650799024                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1282                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1271                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 348171673                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            540080847                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           217272434                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         215393524                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         63213343                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2142982647                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               62293                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1846789239                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1603792                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       612307626                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    971971651                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          61740                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     901816172                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.047856                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.805282                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            901432928                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.245259                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.373096                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                252952155                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             185449202                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 329948666                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49145661                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               83937244                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2290194252                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               83937244                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                289581235                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                42452690                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14732                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 340327979                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             145119048                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2240246263                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3253                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               23409384                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             104435988                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            12914                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2886886923                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6492696422                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6491823897                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            872525                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993077484                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                893809439                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1297                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1279                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 347581498                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            540130264                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           217339026                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         215698631                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         63624557                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2143116411                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               61984                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1846710444                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1594990                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       612455576                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1230055220                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          61431                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     901432928                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.048639                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.805034                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           246447632     27.33%     27.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           157137359     17.42%     44.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           150782303     16.72%     61.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           147402025     16.35%     77.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           103278327     11.45%     89.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            58944184      6.54%     95.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            27765839      3.08%     98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             9016087      1.00%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1042416      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           246353789     27.33%     27.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           156616036     17.37%     44.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           150729221     16.72%     61.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           147768172     16.39%     77.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           103385508     11.47%     89.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            58828894      6.53%     95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            27652970      3.07%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9059576      1.01%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1038762      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       901816172                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       901432928                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2649753     16.80%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9923154     62.91%     79.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3201078     20.29%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2653442     16.77%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9987443     63.11%     79.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3184017     20.12%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2725633      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1219452054     66.03%     66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2723282      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1219442774     66.03%     66.18% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.18% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.18% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.18% # Type of FU issued
@@ -180,86 +182,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.18% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            447143707     24.21%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           177467845      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            447111847     24.21%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           177432541      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1846789239                       # Type of FU issued
-system.cpu.iq.rate                           2.006909                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15773985                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008541                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4612764501                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2755319104                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1806286815                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                7926                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             295108                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          254                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1859834785                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    2806                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        168142861                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1846710444                       # Type of FU issued
+system.cpu.iq.rate                           2.007566                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15824902                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008569                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4612265736                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2755596507                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1806213833                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                7972                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             299756                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          262                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1859809264                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    2800                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        168051220                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    155978687                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       426493                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       273307                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     68112538                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    156028104                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       428762                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       273999                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     68179105                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         6604                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             5                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         6544                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               83923326                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7067341                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1165909                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2143044940                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2779083                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             540080847                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            217272723                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5880                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 921481                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 15876                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         273307                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10083404                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5246002                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             15329406                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1818781271                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             438673892                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          28007968                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               83937244                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 7052726                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1164788                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2143178395                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2770813                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             540130264                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            217339290                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5780                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 918370                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 16344                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         273999                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10084956                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5239444                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             15324400                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1818728049                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             438648218                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          27982395                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    610552632                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                170822936                       # Number of branches executed
-system.cpu.iew.exec_stores                  171878740                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.976472                       # Inst execution rate
-system.cpu.iew.wb_sent                     1813583044                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1806287069                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1379599827                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2050187147                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    610505515                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                170830738                       # Number of branches executed
+system.cpu.iew.exec_stores                  171857297                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.977147                       # Inst execution rate
+system.cpu.iew.wb_sent                     1813502289                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1806214095                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1379770015                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2939115294                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.962895                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.672914                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.963543                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.469451                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       614080092                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       614215075                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14315856                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    817892846                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.869424                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.327438                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14315916                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    817495684                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.870333                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.327982                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    301647537     36.88%     36.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    204220955     24.97%     61.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     73668560      9.01%     70.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     95020529     11.62%     82.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     30882746      3.78%     86.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28791442      3.52%     89.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     16321974      2.00%     91.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11763768      1.44%     93.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     55575335      6.79%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    301315612     36.86%     36.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    204371597     25.00%     61.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     73328146      8.97%     70.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     95079836     11.63%     82.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     30908814      3.78%     86.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28772319      3.52%     89.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     16400347      2.01%     91.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11729678      1.43%     93.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     55589335      6.80%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    817892846                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    817495684                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -270,63 +272,62 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              55575335                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              55589335                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2905386359                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4370176424                       # The number of ROB writes
-system.cpu.timesIdled                          410524                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        18399678                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2905110180                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4370460169                       # The number of ROB writes
+system.cpu.timesIdled                          411218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        18442224                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
-system.cpu.cpi                               1.112881                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.112881                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.898569                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.898569                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3086863683                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1679046201                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       253                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1001956200                       # number of misc regfile reads
-system.cpu.icache.replacements                  10582                       # number of replacements
-system.cpu.icache.tagsinuse                994.041407                       # Cycle average of tags in use
-system.cpu.icache.total_refs                183174422                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  12099                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               15139.633193                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.112469                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.112469                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.898901                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.898901                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4004380463                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2286341091                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       262                       # number of floating regfile reads
+system.cpu.misc_regfile_reads              1001920300                       # number of misc regfile reads
+system.cpu.icache.replacements                  10653                       # number of replacements
+system.cpu.icache.tagsinuse                997.180863                       # Cycle average of tags in use
+system.cpu.icache.total_refs                183252097                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  12174                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               15052.743305                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     994.041407                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.485372                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.485372                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    183181303                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       183181303                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     183181303                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        183181303                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    183181303                       # number of overall hits
-system.cpu.icache.overall_hits::total       183181303                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       224498                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        224498                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       224498                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         224498                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       224498                       # number of overall misses
-system.cpu.icache.overall_misses::total        224498                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1640944500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1640944500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1640944500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1640944500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1640944500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1640944500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    183405801                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    183405801                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    183405801                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    183405801                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    183405801                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    183405801                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001224                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001224                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001224                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  7309.394738                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  7309.394738                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  7309.394738                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     997.180863                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.486905                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.486905                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    183258482                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       183258482                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     183258482                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        183258482                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    183258482                       # number of overall hits
+system.cpu.icache.overall_hits::total       183258482                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       224389                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        224389                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       224389                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         224389                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       224389                       # number of overall misses
+system.cpu.icache.overall_misses::total        224389                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1641701500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1641701500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1641701500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1641701500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1641701500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1641701500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    183482871                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    183482871                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    183482871                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    183482871                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    183482871                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    183482871                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001223                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001223                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001223                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  7316.318982                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  7316.318982                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  7316.318982                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -337,80 +338,80 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
 system.cpu.icache.writebacks::total                 8                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2528                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2528                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2528                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2528                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2528                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2528                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       221970                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       221970                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       221970                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       221970                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       221970                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       221970                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    915300500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    915300500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    915300500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    915300500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    915300500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    915300500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2536                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       221853                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst       221853                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst       221853                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       221853                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    915847000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    915847000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    915847000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    915847000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001209                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001209                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001209                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4128.170455                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4128.170455                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4128.170455                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2526943                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.013788                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                415067708                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2531039                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 163.991036                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2117980000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.013788                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997806                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997806                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    266225231                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       266225231                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148171071                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148171071                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     414396302                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414396302                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414396302                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414396302                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2666540                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2666540                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       989130                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       989130                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3655670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3655670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3655670                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3655670                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  38988147500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  38988147500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  20140670500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20140670500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  59128818000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  59128818000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  59128818000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  59128818000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    268891771                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    268891771                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2527239                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.019700                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                415133448                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2531335                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.997830                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2117139000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.019700                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997808                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997808                       # Average percentage of cache occupancy
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 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418051972                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418051972                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418051972                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418051972                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009917                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006631                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008745                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008745                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    418117752                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418117752                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418117752                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418117752                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009926                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006630                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008750                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008750                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,126 +420,126 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2228961                       # number of writebacks
-system.cpu.dcache.writebacks::total           2228961                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       905583                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       905583                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9205                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         9205                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       914788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       914788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       914788                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       914788                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760957                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1760957                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       979925                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       979925                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2740882                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2740882                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2740882                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2740882                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14913752500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  14913752500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17128067500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17128067500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32041820000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  32041820000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32041820000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  32041820000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006549                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006570                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.writebacks::writebacks      2229248                       # number of writebacks
+system.cpu.dcache.writebacks::total           2229248                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       908413                       # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total         9153                       # number of WriteReq MSHR hits
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total  14912272500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17125192000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17125192000                       # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total  32037464500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total  32037464500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006548                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006569                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8469.117928                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.957573                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11690.331798                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11690.331798                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8467.243688                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                574923                       # number of replacements
-system.cpu.l2cache.tagsinuse             21610.762617                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3193774                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                594114                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.375692                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          253017747000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 13759.541955                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     63.216767                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   7788.003895                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.419908                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001929                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.237671                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.659508                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         6104                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1427022                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1433126                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2228969                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2228969                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1305                       # number of UpgradeReq hits
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+system.cpu.l2cache.avg_refs                  5.377056                       # Average number of references to valid blocks.
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -547,50 +548,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.490563                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.189057                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.993847                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.320333                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.490563                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229051                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.490563                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229051                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 83c21c0e9..f6abc7cbb 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -103,9 +103,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index 6ca36871d..bd9171025 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:55:18
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:57
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4c0e660f2..90f786dd4 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229360000                       # Number of ticks simulated
 final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 614441                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1136170                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              657801730                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219436                       # Number of bytes of host memory used
-host_seconds                                  1345.74                       # Real time elapsed on the host
+host_inst_rate                                 552274                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1021217                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              591247536                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269460                       # Number of bytes of host memory used
+host_seconds                                  1497.22                       # Real time elapsed on the host
 sim_insts                                   826877145                       # Number of instructions simulated
 sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 10832432532                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1528317615                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          3581460239                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          4441632806                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1993077484                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     533262345                       # number of memory refs
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 557746b22..2697e7cd5 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -185,9 +185,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index d62454745..a1341a25f 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:56:26
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:10:10
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 235d6de24..b16b4826d 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.658730                       # Nu
 sim_ticks                                1658729604000                       # Number of ticks simulated
 final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 332704                       # Simulator instruction rate (inst/s)
-host_op_rate                                   615206                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              667409022                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228396                       # Number of bytes of host memory used
-host_seconds                                  2485.33                       # Real time elapsed on the host
+host_inst_rate                                 376518                       # Simulator instruction rate (inst/s)
+host_op_rate                                   696225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              755302226                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278396                       # Number of bytes of host memory used
+host_seconds                                  2196.11                       # Real time elapsed on the host
 sim_insts                                   826877145                       # Number of instructions simulated
 sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1528317615                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          3581460239                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          4441632806                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1993077484                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     533262345                       # number of memory refs
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 896780d15..b16c136ab 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -103,7 +103,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 4ac95340c..291a38eb7 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:57:51
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:57
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 0122786be..af3b62cfc 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007259500                       # Number of ticks simulated
 final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 632359                       # Simulator instruction rate (inst/s)
-host_op_rate                                   985272                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              598287574                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215392                       # Number of bytes of host memory used
-host_seconds                                  4756.92                       # Real time elapsed on the host
+host_inst_rate                                 825244                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1285805                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              780780219                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265452                       # Number of bytes of host memory used
+host_seconds                                  3645.08                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 37129731755                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   4686862580                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads         11558008181                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_int_register_reads         14165752762                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         6716691823                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                    1677713086                       # number of memory refs
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 8676306dc..5366c30ec 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -185,7 +185,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index a0492ef0b..f085076c6 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:58:27
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:07:40
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 87097d7a4..1ff8843da 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.923548                       # Nu
 sim_ticks                                5923548078000                       # Number of ticks simulated
 final_tick                               5923548078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 443317                       # Simulator instruction rate (inst/s)
-host_op_rate                                   690728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              872984671                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224336                       # Number of bytes of host memory used
-host_seconds                                  6785.40                       # Real time elapsed on the host
+host_inst_rate                                 557700                       # Simulator instruction rate (inst/s)
+host_op_rate                                   868947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1098229805                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274380                       # Number of bytes of host memory used
+host_seconds                                  5393.72                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   173910080                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   4686862580                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads         11558008181                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_int_register_reads         14165752762                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         6716691823                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                    1677713086                       # number of memory refs
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 91cbfaf86..ae31ca40a 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -516,7 +516,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 6d5fbd5bb..dc48832a4 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 16:00:57
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:57
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -24,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 87727531000 because target called exit()
+122 123 124 Exiting @ tick 87751730000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 19ddbed23..247b6d16f 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,159 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.087728                       # Number of seconds simulated
-sim_ticks                                 87727531000                       # Number of ticks simulated
-final_tick                                87727531000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.087752                       # Number of seconds simulated
+sim_ticks                                 87751730000                       # Number of ticks simulated
+final_tick                                87751730000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36137                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60569                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               24003841                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234992                       # Number of bytes of host memory used
-host_seconds                                  3654.73                       # Real time elapsed on the host
+host_inst_rate                                  34298                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57486                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               22788458                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285268                       # Number of bytes of host memory used
+host_seconds                                  3850.71                       # Real time elapsed on the host
 sim_insts                                   132071227                       # Number of instructions simulated
 sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      345792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 220224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read                      345024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 219584                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         5403                       # Number of read requests responded to by this memory
+system.physmem.num_reads                         5391                       # Number of read requests responded to by this memory
 system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3941659                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   2510318                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       3941659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                        3931820                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2502332                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3931820                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        175455063                       # number of cpu cycles simulated
+system.cpu.numCycles                        175503461                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 20916443                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           20916443                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2209285                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              15543482                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 13847483                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 20929970                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           20929970                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2208761                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15515509                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 13857635                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           27331578                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      227091825                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20916443                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13847483                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59872682                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                19479342                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               71171142                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 1142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          9711                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  25826236                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                465691                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          175377754                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.138493                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.301400                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27320294                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      226942709                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20929970                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13857635                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59854483                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                19459786                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               71271521                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  647                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5211                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  25822554                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                471165                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          175426420                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.136612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.300359                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                117181647     66.82%     66.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3214918      1.83%     68.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2487615      1.42%     70.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3152390      1.80%     71.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3541045      2.02%     73.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3761465      2.14%     76.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4534795      2.59%     78.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2814480      1.60%     80.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 34689399     19.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                117249103     66.84%     66.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3234615      1.84%     68.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2477718      1.41%     70.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3147881      1.79%     71.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3542128      2.02%     73.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3766355      2.15%     76.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4530628      2.58%     78.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2823565      1.61%     80.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 34654427     19.75%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            175377754                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.119213                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.294302                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40655078                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              60979767                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46580847                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10170563                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               16991499                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              366154541                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               16991499                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 48551575                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                16255360                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          22908                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  48159937                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              45396475                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              356930622                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    31                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20611614                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22556100                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           370578330                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             915376002                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        905357204                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          10018798                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                136214921                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1884                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1879                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  95075204                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             89798900                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            33126150                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59105892                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         19470251                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  344622515                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                7679                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 271009025                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            252543                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       122771831                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    234148079                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           6433                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     175377754                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.545287                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.468253                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            175426420                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.119257                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.293095                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40654970                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              61059749                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46547974                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10189463                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               16974264                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              365977737                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               16974264                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 48548849                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                16319097                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          23046                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  48140036                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              45421128                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              356799059                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    33                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20636040                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22537767                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             2198                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           506554560                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1130537576                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1120266829                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10270747                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             320143989                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                186410571                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1911                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1906                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  95097015                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89808446                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            33130186                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          59201466                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         19519303                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  344515408                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                7842                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 270869041                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            254270                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       122674827                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    297005948                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           6596                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     175426420                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.544061                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.467197                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            49123743     28.01%     28.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            52511910     29.94%     57.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34319849     19.57%     77.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            19020528     10.85%     88.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12714994      7.25%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4949443      2.82%     98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2083502      1.19%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              542650      0.31%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              111135      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            49131918     28.01%     28.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            52597598     29.98%     57.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34344441     19.58%     77.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18981959     10.82%     88.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12711399      7.25%     95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4926918      2.81%     98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2079867      1.19%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              541264      0.31%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              111056      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       175377754                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       175426420                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   91290      3.51%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2230006     85.80%     89.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                277845     10.69%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   91065      3.49%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2241508     85.86%     89.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                277930     10.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212979      0.45%      0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             176351426     65.07%     65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1212815      0.45%      0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             176257528     65.07%     65.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1596977      0.59%     66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1592327      0.59%     66.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.11% # Type of FU issued
@@ -179,86 +180,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.11% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             68342169     25.22%     91.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23505474      8.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68300084     25.22%     91.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23506287      8.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              271009025                       # Type of FU issued
-system.cpu.iq.rate                           1.544606                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2599141                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009591                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          714934206                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         462829464                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    263397424                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5313282                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4873666                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2553131                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              269732632                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2662555                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18949841                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              270869041                       # Type of FU issued
+system.cpu.iq.rate                           1.543383                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2610503                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009638                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          714724682                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         462639790                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    263265519                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5304593                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4857798                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2549095                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              269608691                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2658038                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18925158                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     33149310                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        29835                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       306343                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     12610434                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     33158856                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        30567                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       304625                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12614470                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        47714                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        47486                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               16991499                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  515293                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                247384                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           344630194                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            299081                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              89798900                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             33126150                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1841                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 161274                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 32917                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         306343                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1299828                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1028827                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2328655                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             267903545                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              67266011                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3105480                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               16974264                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  523635                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                253200                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           344523250                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            297274                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              89808446                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             33130186                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1859                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 168556                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 31575                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         304625                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1298513                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1028751                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2327264                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             267763849                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              67223329                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3105192                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     90381113                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14784987                       # Number of branches executed
-system.cpu.iew.exec_stores                   23115102                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.526907                       # Inst execution rate
-system.cpu.iew.wb_sent                      266831657                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     265950555                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 214539100                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 362277288                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     90337843                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14773998                       # Number of branches executed
+system.cpu.iew.exec_stores                   23114514                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.525690                       # Inst execution rate
+system.cpu.iew.wb_sent                      266689649                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     265814614                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 214459238                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 504388651                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.515776                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.592196                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.514583                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.425186                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      132071227                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       123379420                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       123271968                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2210265                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158386255                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.397615                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.796088                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           2209353                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158452156                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.397034                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.794480                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     54200924     34.22%     34.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     60421756     38.15%     72.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15533803      9.81%     82.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12711410      8.03%     90.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4532649      2.86%     93.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2958963      1.87%     94.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2077692      1.31%     96.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1244602      0.79%     97.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4704456      2.97%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     54225216     34.22%     34.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     60443910     38.15%     72.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15544008      9.81%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12710691      8.02%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4546278      2.87%     93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2974927      1.88%     94.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2086566      1.32%     96.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1244605      0.79%     97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4675955      2.95%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158386255                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158452156                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071227                       # Number of instructions committed
 system.cpu.commit.committedOps              221363017                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -269,64 +270,64 @@ system.cpu.commit.branches                   12326943                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4704456                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4675955                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    498424236                       # The number of ROB reads
-system.cpu.rob.rob_writes                   706514017                       # The number of ROB writes
-system.cpu.timesIdled                            1681                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           77309                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    498411186                       # The number of ROB reads
+system.cpu.rob.rob_writes                   706281673                       # The number of ROB writes
+system.cpu.timesIdled                            1684                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           77041                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071227                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363017                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             132071227                       # Number of Instructions Simulated
-system.cpu.cpi                               1.328488                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.328488                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.752735                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.752735                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                511675262                       # number of integer regfile reads
-system.cpu.int_regfile_writes               274174484                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3515494                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2227241                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               139504609                       # number of misc regfile reads
+system.cpu.cpi                               1.328855                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.328855                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.752528                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.752528                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                657510090                       # number of integer regfile reads
+system.cpu.int_regfile_writes               365370199                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3509073                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2221147                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               139423581                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.icache.replacements                   5602                       # number of replacements
-system.cpu.icache.tagsinuse               1631.479553                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 25817139                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7573                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                3409.103262                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   5601                       # number of replacements
+system.cpu.icache.tagsinuse               1627.936468                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25813461                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7571                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                3409.518029                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1631.479553                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.796621                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.796621                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     25817139                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25817139                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25817139                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25817139                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25817139                       # number of overall hits
-system.cpu.icache.overall_hits::total        25817139                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9097                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9097                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9097                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9097                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9097                       # number of overall misses
-system.cpu.icache.overall_misses::total          9097                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    188035000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    188035000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    188035000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    188035000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    188035000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    188035000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25826236                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25826236                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25826236                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25826236                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25826236                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25826236                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1627.936468                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.794891                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.794891                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25813461                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25813461                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25813461                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25813461                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25813461                       # number of overall hits
+system.cpu.icache.overall_hits::total        25813461                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9093                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9093                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9093                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9093                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9093                       # number of overall misses
+system.cpu.icache.overall_misses::total          9093                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    187306000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    187306000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    187306000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    187306000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    187306000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    187306000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25822554                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25822554                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25822554                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25822554                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25822554                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25822554                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000352                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000352                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000352                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -335,80 +336,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1378                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1378                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1378                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1378                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1378                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1378                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7719                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7719                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7719                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7719                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7719                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7719                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130954500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    130954500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130954500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    130954500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130954500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    130954500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1367                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1367                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1367                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1367                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1367                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1367                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7726                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7726                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7726                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7726                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7726                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7726                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130634500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    130634500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130634500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    130634500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130634500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    130634500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     54                       # number of replacements
-system.cpu.dcache.tagsinuse               1429.840369                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 68659767                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1998                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               34364.247748                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     56                       # number of replacements
+system.cpu.dcache.tagsinuse               1426.584624                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 68642098                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1997                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               34372.607912                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1429.840369                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.349082                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.349082                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     48145557                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        48145557                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514023                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514023                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68659580                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68659580                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68659580                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68659580                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          765                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           765                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1707                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1707                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2472                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2472                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2472                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2472                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24609000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     24609000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     64758500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     64758500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     89367500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     89367500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     89367500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     89367500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     48146322                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     48146322                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    1426.584624                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.348287                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.348287                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     48127880                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        48127880                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514014                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514014                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68641894                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68641894                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68641894                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68641894                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          772                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           772                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1716                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1716                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2488                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2488                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2488                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2488                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24823500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24823500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     65115000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     65115000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     89938500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     89938500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     89938500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     89938500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     48128652                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     48128652                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     68662052                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     68662052                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     68662052                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     68662052                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     68644382                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     68644382                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     68644382                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     68644382                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000016                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000084                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000036                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000036                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,119 +420,119 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
 system.cpu.dcache.writebacks::total                13                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          323                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          323                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          331                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          331                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            3                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            3                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          326                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          442                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          442                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1704                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1704                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2146                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     14613500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     14613500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59538000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     59538000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     74151500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     74151500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     74151500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     74151500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data          334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          334                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          334                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          441                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          441                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1713                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1713                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2154                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2154                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2154                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2154                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     14546500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     14546500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59868000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     59868000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     74414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     74414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     74414500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     74414500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000083                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33062.217195                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34940.140845                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34553.355079                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34553.355079                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2591.074934                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    4164                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3853                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  1.080716                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2579.336511                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    4173                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3841                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.086436                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     1.913608                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2287.446518                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    301.714808                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.000058                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.069807                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.009208                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.079073                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4132                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           30                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           4162                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks     1.713269                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2279.819240                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    297.804001                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000052                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.069575                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.009088                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.078715                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         4140                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           31                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           4171                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4132                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           38                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            4170                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4132                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           38                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           4170                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3441                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          411                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3852                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          146                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          146                       # number of UpgradeReq misses
+system.cpu.l2cache.demand_hits::cpu.inst         4140                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           39                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            4179                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4140                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           39                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           4179                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3431                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          409                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3840                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          155                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          155                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1551                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1551                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3441                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1962                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5403                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3441                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1962                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5403                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117870000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14049500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    131919500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     52980000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     52980000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    117870000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     67029500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    184899500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    117870000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     67029500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    184899500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7573                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          441                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         8014                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         3431                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1960                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5391                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3431                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1960                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5391                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117518500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     13976500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    131495000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     52996000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     52996000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    117518500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     66972500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    184491000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    117518500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     66972500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    184491000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7571                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          440                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         8011                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          146                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          146                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          155                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          155                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1559                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1559                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7573                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2000                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9573                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7573                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2000                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9573                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.454377                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.931973                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         7571                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1999                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9570                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7571                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1999                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9570                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.453177                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.929545                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994869                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.454377                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.981000                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.454377                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.981000                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.453177                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980490                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.453177                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980490                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -540,48 +541,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3441                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          411                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3852                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          146                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          146                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3431                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          409                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3840                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          155                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          155                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1551                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1551                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3441                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1962                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3441                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1962                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5403                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106751500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12743500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    119495000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4526000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4526000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48112000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48112000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106751500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     60855500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    167607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106751500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     60855500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    167607000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.454377                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.931973                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3431                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1960                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5391                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3431                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1960                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5391                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106440500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12676500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    119117000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4805000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4805000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48110500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48110500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106440500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     60787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    167227500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106440500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     60787000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    167227500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.453177                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.929545                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994869                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.454377                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.981000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.454377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.981000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.453177                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980490                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.453177                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980490                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 8039a1c87..774020e98 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -103,7 +103,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 8d8c9ffed..776b4fadc 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 16:01:40
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:08:43
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 8ac81bf15..be9f62e84 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393100000                       # Number of ticks simulated
 final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 595335                       # Simulator instruction rate (inst/s)
-host_op_rate                                   997834                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              592278441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222596                       # Number of bytes of host memory used
-host_seconds                                   221.84                       # Real time elapsed on the host
+host_inst_rate                                 449336                       # Simulator instruction rate (inst/s)
+host_op_rate                                   753127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              447028889                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272700                       # Number of bytes of host memory used
+host_seconds                                   293.93                       # Real time elapsed on the host
 sim_insts                                   132071228                       # Number of instructions simulated
 sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1698379042                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    220339607                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           567557364                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           705008819                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          318312586                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      77165306                       # number of memory refs
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 4785eec61..8ab20ef21 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -185,7 +185,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index b246803c9..483a9fc09 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 16:03:05
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 4699fa0ff..029c5536e 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250961                       # Nu
 sim_ticks                                250960631000                       # Number of ticks simulated
 final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 334930                       # Simulator instruction rate (inst/s)
-host_op_rate                                   561373                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              636431760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231532                       # Number of bytes of host memory used
-host_seconds                                   394.32                       # Real time elapsed on the host
+host_inst_rate                                 291052                       # Simulator instruction rate (inst/s)
+host_op_rate                                   487829                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              553054781                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 281636                       # Number of bytes of host memory used
+host_seconds                                   453.77                       # Real time elapsed on the host
 sim_insts                                   132071228                       # Number of instructions simulated
 sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      303040                       # Number of bytes read from this memory
@@ -32,8 +32,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    220339607                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           567557364                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           705008819                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          318312586                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      77165306                       # number of memory refs
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index d5bc006d3..784b98c30 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 memories=system.physmem
@@ -936,7 +936,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -956,7 +956,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index f8c61dd9a..424a8fb50 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:18
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:57
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 03b343541..6f54e627b 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 720353                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1474974                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18429520570                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355156                       # Number of bytes of host memory used
-host_seconds                                   277.38                       # Real time elapsed on the host
+host_inst_rate                                 514394                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1053258                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13160254594                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404120                       # Number of bytes of host memory used
+host_seconds                                   388.45                       # Real time elapsed on the host
 sim_insts                                   199813913                       # Number of instructions simulated
 sim_ops                                     409133277                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
@@ -187,8 +187,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     39954968                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    374297244                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           801267455                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          401624559                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          1159024883                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          636431619                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      35626519                       # number of memory refs
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 5b2a3d4f5..cb842a83c 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -932,7 +932,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -952,7 +952,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 5fdad8343..04d54d050 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:18
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:04:51
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 68bf4f343..7f3f31ab7 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.195470                       # Nu
 sim_ticks                                5195470393000                       # Number of ticks simulated
 final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 387917                       # Simulator instruction rate (inst/s)
-host_op_rate                                   744582                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14589799311                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351980                       # Number of bytes of host memory used
-host_seconds                                   356.10                       # Real time elapsed on the host
+host_inst_rate                                 457894                       # Simulator instruction rate (inst/s)
+host_op_rate                                   878898                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17221658168                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 400980                       # Number of bytes of host memory used
+host_seconds                                   301.68                       # Real time elapsed on the host
 sim_insts                                   138138472                       # Number of instructions simulated
 sim_ops                                     265147881                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
@@ -331,8 +331,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts     24882695                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    249556386                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           543487907                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          266037487                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           778081993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          422921187                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      23169904                       # number of memory refs
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 1666732e2..c82cb42ab 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -516,7 +516,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 9c9739cf4..b715ba6b6 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:49:56
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:03:20
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 12299500 because target called exit()
+Exiting @ tick 12198000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index cb09e3c8e..f253ef45b 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12299500                       # Number of ticks simulated
-final_tick                                   12299500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12198000                       # Number of ticks simulated
+final_tick                                   12198000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24245                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43905                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55046151                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223460                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  10821                       # Simulator instruction rate (inst/s)
+host_op_rate                                    19598                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               24369729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271424                       # Number of bytes of host memory used
+host_seconds                                     0.50                       # Real time elapsed on the host
 sim_insts                                        5416                       # Number of instructions simulated
 sim_ops                                          9809                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28864                       # Number of bytes read from this memory
@@ -17,248 +17,249 @@ system.physmem.bytes_written                        0                       # Nu
 system.physmem.num_reads                          451                       # Number of read requests responded to by this memory
 system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2346762063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1571445994                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2346762063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                     2366289556                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1584522053                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2366289556                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            24600                       # number of cpu cycles simulated
+system.cpu.numCycles                            24397                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     3225                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3225                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                566                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2653                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      811                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     3206                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3206                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                560                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2627                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      792                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7427                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15574                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3225                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                811                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4199                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2532                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   3117                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   33                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           203                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1968                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   283                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              16907                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.630863                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.070076                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               7375                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15410                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3206                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                792                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4170                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2487                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   3163                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   16                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            98                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1951                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   281                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              16727                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.635918                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.075272                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    12804     75.73%     75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      179      1.06%     76.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      164      0.97%     77.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      216      1.28%     79.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      176      1.04%     80.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      185      1.09%     81.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      253      1.50%     82.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      169      1.00%     83.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2761     16.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    12659     75.68%     75.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      177      1.06%     76.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      166      0.99%     77.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      214      1.28%     79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      171      1.02%     80.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      175      1.05%     81.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      250      1.49%     82.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      166      0.99%     83.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2749     16.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                16907                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.131098                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.633089                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7993                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3065                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3795                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   126                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1928                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  26201                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1928                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8331                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1936                       # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total                16727                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.131410                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.631635                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7836                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3109                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3749                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   128                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1905                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  26025                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1905                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8180                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1960                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            442                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3571                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   699                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  24623                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      3522                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   718                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24463                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     40                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   586                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               22939                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 51440                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            51424                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                     50                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   591                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands               35223                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 70482                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            70466                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    13571                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps                 14707                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                    20516                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             33                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1885                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2380                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1795                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      1918                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2376                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1791                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21756                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  39                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17955                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                74                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11342                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        13993                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             26                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         16907                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.061986                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.892645                       # Number of insts issued each cycle
+system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      21692                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  38                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17854                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                82                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11255                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        20549                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             25                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         16727                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.067376                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.893384                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11435     67.63%     67.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1387      8.20%     75.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1028      6.08%     81.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 682      4.03%     85.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 697      4.12%     90.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 717      4.24%     94.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 667      3.95%     98.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 261      1.54%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11276     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1383      8.27%     75.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1035      6.19%     81.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 667      3.99%     85.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 692      4.14%     89.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 723      4.32%     94.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 673      4.02%     98.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 245      1.46%     99.80% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  33      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           16907                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           16727                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     147     74.24%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     74.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     30     15.15%     89.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    21     10.61%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     140     73.30%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     30     15.71%     89.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    21     10.99%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14483     80.66%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1993     11.10%     91.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1475      8.21%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14397     80.64%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1982     11.10%     91.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1471      8.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17955                       # Type of FU issued
-system.cpu.iq.rate                           0.729878                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         198                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011028                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              53081                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             33143                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16452                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17854                       # Type of FU issued
+system.cpu.iq.rate                           0.731811                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         191                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010698                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              52700                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32991                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16402                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18145                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  18037                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              152                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              151                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1324                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses           24                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1320                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           20                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           11                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          857                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1928                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                   1905                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                    1329                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    36                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21795                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2380                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1795                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 35                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewUnblockCycles                    39                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21730                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                24                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2376                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1791                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     10                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             63                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          653                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  716                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16888                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1847                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1067                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             59                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          631                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  690                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16824                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1844                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1030                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3212                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1649                       # Number of branches executed
-system.cpu.iew.exec_stores                       1365                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.686504                       # Inst execution rate
-system.cpu.iew.wb_sent                          16662                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16456                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10670                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     15796                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3203                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1645                       # Number of branches executed
+system.cpu.iew.exec_stores                       1359                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.689593                       # Inst execution rate
+system.cpu.iew.wb_sent                          16593                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16406                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10679                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     24448                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.668943                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.675487                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.672460                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.436805                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5416                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             9809                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           11985                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           11920                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               593                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        14979                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.654850                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.499757                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               571                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        14822                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.661787                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.507902                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11331     75.65%     75.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1373      9.17%     84.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          652      4.35%     89.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          726      4.85%     94.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          372      2.48%     96.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          130      0.87%     97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          138      0.92%     98.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           68      0.45%     98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          189      1.26%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11181     75.44%     75.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1365      9.21%     84.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          653      4.41%     89.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          730      4.93%     93.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          365      2.46%     96.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          129      0.87%     97.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          139      0.94%     98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           71      0.48%     98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          189      1.28%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        14979                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14822                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5416                       # Number of instructions committed
 system.cpu.commit.committedOps                   9809                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -271,60 +272,60 @@ system.cpu.commit.int_insts                      9714                       # Nu
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   189                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        36584                       # The number of ROB reads
-system.cpu.rob.rob_writes                       45550                       # The number of ROB writes
+system.cpu.rob.rob_reads                        36362                       # The number of ROB reads
+system.cpu.rob.rob_writes                       45397                       # The number of ROB writes
 system.cpu.timesIdled                             150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            7693                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            7670                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5416                       # Number of Instructions Simulated
 system.cpu.committedOps                          9809                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5416                       # Number of Instructions Simulated
-system.cpu.cpi                               4.542097                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.542097                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.220163                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.220163                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    24791                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   15157                       # number of integer regfile writes
+system.cpu.cpi                               4.504616                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.504616                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.221995                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.221995                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    35454                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   22063                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7406                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7402                       # number of misc regfile reads
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                146.671178                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1576                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                145.636183                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1561                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    304                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.184211                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.134868                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     146.671178                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.071617                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.071617                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1576                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1576                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1576                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1576                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1576                       # number of overall hits
-system.cpu.icache.overall_hits::total            1576                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          392                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           392                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          392                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            392                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          392                       # number of overall misses
-system.cpu.icache.overall_misses::total           392                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     13905000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     13905000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     13905000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     13905000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     13905000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     13905000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1968                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1968                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1968                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1968                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1968                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199187                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.199187                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.199187                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     145.636183                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.071111                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.071111                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1561                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1561                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1561                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1561                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1561                       # number of overall hits
+system.cpu.icache.overall_hits::total            1561                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          390                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           390                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          390                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            390                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          390                       # number of overall misses
+system.cpu.icache.overall_misses::total           390                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     13866500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     13866500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     13866500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     13866500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     13866500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     13866500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1951                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1951                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1951                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1951                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1951                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1951                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199897                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.199897                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.199897                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -333,40 +334,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           88                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           88                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           88                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           88                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           88                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           88                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           86                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           86                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          304                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          304                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          304                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          304                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          304                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          304                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10684500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     10684500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10684500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     10684500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10684500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     10684500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.154472                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.154472                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.154472                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     10687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     10687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10687000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     10687000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 85.091432                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 84.751522                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     2365                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    148                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  15.979730                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      85.091432                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020774                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020774                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      84.751522                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020691                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020691                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1507                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1507                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
@@ -375,38 +376,38 @@ system.cpu.dcache.demand_hits::cpu.data          2365                       # nu
 system.cpu.dcache.demand_hits::total             2365                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data         2365                       # number of overall hits
 system.cpu.dcache.overall_hits::total            2365                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          117                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           117                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          193                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            193                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          193                       # number of overall misses
-system.cpu.dcache.overall_misses::total           193                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4056500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4056500                       # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data          191                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            191                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          191                       # number of overall misses
+system.cpu.dcache.overall_misses::total           191                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4030500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4030500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data      2917500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      2917500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      6974000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      6974000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      6974000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      6974000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1624                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1624                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data      6948000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      6948000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      6948000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      6948000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1622                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1622                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2558                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2558                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2558                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2558                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.072044                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2556                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2556                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2556                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2556                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070900                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.075450                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.075450                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074726                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074726                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -415,12 +416,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           44                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           44                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           44                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           44                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           42                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           42                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           42                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           42                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           73                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           73                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
@@ -429,34 +430,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          149
 system.cpu.dcache.demand_mshr_misses::total          149                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          149                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2572000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2572000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2574000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2574000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2689500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2689500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5261500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5261500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5261500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5261500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5263500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5263500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5263500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5263500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058249                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058249                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35232.876712                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35312.080537                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35312.080537                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               180.810821                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               179.622577                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   374                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005348                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    146.260836                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     34.549985                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004464                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001054                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005518                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    145.234150                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     34.388427                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004432                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001049                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005482                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -474,17 +475,17 @@ system.cpu.l2cache.demand_misses::total           451                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          302                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          149                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          451                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10365500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10368000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2486500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     12852000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     12854500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2603000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2603000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     10365500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     10368000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      5089500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     15455000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     10365500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     15457500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     10368000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      5089500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     15455000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     15457500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          304                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           73                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          377                       # number of ReadReq accesses(hits+misses)
@@ -503,12 +504,12 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993421
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993421                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34250                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -529,17 +530,17 @@ system.cpu.l2cache.demand_mshr_misses::total          451
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          451                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9393500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2262000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11655500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9394000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2263500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11657500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2369500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2369500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4631500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14025000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9393500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4631500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14025000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9394000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4633000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14027000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9394000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4633000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14027000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
@@ -547,13 +548,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993421
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index c00e48a14..8422307f0 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -103,7 +103,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 972a98347..4c14d0aa7 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:49:56
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:10:03
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 0f9f946d6..9d71bb46a 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5651000                       # Number of ticks simulated
 final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330960                       # Simulator instruction rate (inst/s)
-host_op_rate                                   598371                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              344132346                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213012                       # Number of bytes of host memory used
+host_inst_rate                                 288907                       # Simulator instruction rate (inst/s)
+host_op_rate                                   522587                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              300697068                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260908                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9715                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               21313                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29928                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          1990                       # number of memory refs
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index e879347ff..ab4fb38df 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -99,7 +99,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 442d60f8b..a99abad11 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:50:07
+Real time: May/21/2012 19:13:48
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.37
-Virtual_time_in_minutes: 0.00616667
-Virtual_time_in_hours:   0.000102778
-Virtual_time_in_days:    4.28241e-06
+Virtual_time_in_seconds: 0.46
+Virtual_time_in_minutes: 0.00766667
+Virtual_time_in_hours:   0.000127778
+Virtual_time_in_days:    5.32407e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 52
-mbytes_total: 227.848
-resident_ratio: 0.228223
+mbytes_resident: 53.1328
+mbytes_total: 274.648
+resident_ratio: 0.193486
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -125,11 +125,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 13872
-page_faults: 0
+page_reclaims: 15001
+page_faults: 3
 swaps: 0
 block_inputs: 0
-block_outputs: 88
+block_outputs: 0
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 15a51cba3..ab4279ad8 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:07
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:13:47
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 3c66f2b85..0a683990f 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000276                       # Nu
 sim_ticks                                      276484                       # Number of ticks simulated
 final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46315                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83864                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2363372                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233320                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  40683                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73662                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2075784                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 281244                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
@@ -33,8 +33,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9715                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               21313                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29928                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          1990                       # number of memory refs
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index b01f0f148..dddeed309 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -185,7 +185,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index f6aa045a2..bbf370aff 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:30
-gem5 started May  8 2012 15:50:07
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:09:59
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index bb825e929..2734be727 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28768000                       # Number of ticks simulated
 final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 193646                       # Simulator instruction rate (inst/s)
-host_op_rate                                   350298                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1026195488                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221892                       # Number of bytes of host memory used
+host_inst_rate                                 209143                       # Simulator instruction rate (inst/s)
+host_op_rate                                   378428                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1108849830                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269844                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
@@ -32,8 +32,8 @@ system.cpu.num_func_calls                           0                       # nu
 system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9715                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               21313                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29928                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          1990                       # number of memory refs
-- 
2.30.2