From 0c27708b0a56fb14ed03f840a7632d0a0887fb95 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 12 Apr 2015 20:11:08 +0200 Subject: [PATCH] liteeth/phy/gmii_mii: avoid doubling pads register on TX --- misoclib/com/liteeth/phy/gmii.py | 8 ++++++-- misoclib/com/liteeth/phy/gmii_mii.py | 4 ++-- misoclib/com/liteeth/phy/mii.py | 8 ++++++-- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py index 3d020b92..429eea62 100644 --- a/misoclib/com/liteeth/phy/gmii.py +++ b/misoclib/com/liteeth/phy/gmii.py @@ -4,15 +4,19 @@ from misoclib.com.liteeth.common import * from misoclib.com.liteeth.generic import * class LiteEthPHYGMIITX(Module): - def __init__(self, pads): + def __init__(self, pads, pads_register): self.sink = sink = Sink(eth_phy_description(8)) ### if hasattr(pads, "tx_er"): self.sync += pads.tx_er.eq(0) - self.sync += [ + pads_eq = [ pads.tx_en.eq(sink.stb), pads.tx_data.eq(sink.data) ] + if pads_register: + self.sync += pads_eq + else: + self.comb += pads_eq self.comb += sink.ack.eq(1) class LiteEthPHYGMIIRX(Module): diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py index 91a122d5..b270d462 100644 --- a/misoclib/com/liteeth/phy/gmii_mii.py +++ b/misoclib/com/liteeth/phy/gmii_mii.py @@ -21,11 +21,11 @@ class LiteEthPHYGMIIMIITX(Module): tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)] gmii_tx_pads = Record(tx_pads_layout) - gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads) + gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False) self.submodules += gmii_tx mii_tx_pads = Record(tx_pads_layout) - mii_tx = LiteEthPHYMIITX(mii_tx_pads) + mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False) self.submodules += mii_tx demux = Demultiplexer(eth_phy_description(8), 2) diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py index 0a0b9b40..3f7b48e3 100644 --- a/misoclib/com/liteeth/phy/mii.py +++ b/misoclib/com/liteeth/phy/mii.py @@ -6,7 +6,7 @@ def converter_description(dw): return EndpointDescription(payload_layout, packetized=True) class LiteEthPHYMIITX(Module): - def __init__(self, pads): + def __init__(self, pads, pads_register=True): self.sink = sink = Sink(eth_phy_description(8)) ### if hasattr(pads, "tx_er"): @@ -19,10 +19,14 @@ class LiteEthPHYMIITX(Module): sink.ack.eq(converter.sink.ack), converter.source.ack.eq(1) ] - self.sync += [ + pads_eq = [ pads.tx_en.eq(converter.source.stb), pads.tx_data.eq(converter.source.data) ] + if pads_register: + self.sync += pads_eq + else: + self.comb += pads_eq class LiteEthPHYMIIRX(Module): def __init__(self, pads): -- 2.30.2