From 0c307d8f7eca608544d183c8c3d068a40571676c Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Fri, 14 Nov 2014 20:45:21 +0000 Subject: [PATCH] predicates.md (easy_fp_constant): Delete redunant tests for 0.0. [gcc] 2014-11-14 Michael Meissner * config/rs6000/predicates.md (easy_fp_constant): Delete redunant tests for 0.0. * config/rs6000/vector.md (VEC_R): Move secondary reload support insns to rs6000.md from vector.md. (reload___store): Likewise. (reload___load): Likewise. (vec_reload_and_plus_): Likewise. * config/rs6000/rs6000.md (Fa): New mode attribute to give constraint for the Altivec registers for a type. (RELOAD): New mode iterator for all of the types that have secondary reload address support to load up a base register. (extendsfdf2_fpr): Use correct constraint. (copysign3_fcpsgn): For SFmode, use correct xscpsgndp instruction. (floatsi2_lfiwax): Add support for -mupper-regs-{sf,df}. Generate the non-VSX instruction if all registers were FPRs. Do not use the patterns in vsx.md for scalar operations. (floatsi2_lfiwax_mem): Likewise. (floatunssi2_lfiwzx): Likewise. (floatunssi2_lfiwzx_mem): Likewise. (fix_truncdi2_fctidz): Likewise. (fixuns_truncdi2_fctiduz): Likewise. (fctiwz_): Likewise. (fctiwuz_): Likewise. (friz): Likewise. (floatdidf2_fpr): Likewise. (floatdidf2_mem): Likewise. (floatunsdidf2): Likewise. (floatunsdidf2_fcfidu): Likewise. (floatunsdidf2_mem): Likewise. (floatdisf2_fcfids): Likewise. (floatdisf2_mem): Likewise. (floatdisf2_internal1): Add explicit test for not FCFIDS to make it more obvious that the code is for pre-ISA 2.06 machines. (floatdisf2_internal2): Likewise. (floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}. Generate the non-VSX instruction if all registers were FPRs. Do not use the patterns in vsx.md for scalar operations. (floatunsdisf2_mem): Likewise. (reload___store): Move the reload handlers here from vector.md, and expand the types we generate reload handlers for. (reload___load): Likewise. (vec_reload_and_plus_): Likewise. * config/rs6000/vsx.md (vsx_float2): Only provide the vector forms of the instructions. Move VSX scalar forms to rs6000.md, and add support for -mupper-regs-sf. (vsx_floatuns2): Likewise. (vsx_fix_trunc2): Likewise. (vsx_fixuns_trunc2): Likewise. (vsx_float_fix_2): Delete DF version, rename to vsx_float_fix_v2df2. (vsx_float_fix_v2df2): Likewise. [gcc/testsuite] 2014-11-14 Michael Meissner * gcc.target/powerpc/ppc-fpconv-1.c: Adjust for -mupper-regs-df changes. * gcc.target/powerpc/ppc-fpconv-2.c: Likewise. * gcc.target/powerpc/ppc-fpconv-3.c: Likewise. * gcc.target/powerpc/ppc-fpconv-4.c: Likewise. * gcc.target/powerpc/ppc-fpconv-5.c: Likewise. * gcc.target/powerpc/ppc-fpconv-6.c: Likewise. * gcc.target/powerpc/ppc-fpconv-7.c: Likewise. * gcc.target/powerpc/ppc-fpconv-8.c: Likewise. * gcc.target/powerpc/ppc-fpconv-9.c: Likewise. * gcc.target/powerpc/ppc-fpconv-10.c: Likewise. * gcc.target/powerpc/ppc-round.c: Likewise. From-SVN: r217590 --- gcc/ChangeLog | 59 ++++++ gcc/config/rs6000/predicates.md | 8 - gcc/config/rs6000/rs6000.md | 185 ++++++++++++------ gcc/config/rs6000/vector.md | 47 ----- gcc/config/rs6000/vsx.md | 36 ++-- gcc/testsuite/ChangeLog | 15 ++ .../gcc.target/powerpc/ppc-fpconv-1.c | 12 +- .../gcc.target/powerpc/ppc-fpconv-10.c | 5 +- .../gcc.target/powerpc/ppc-fpconv-2.c | 5 +- .../gcc.target/powerpc/ppc-fpconv-3.c | 9 +- .../gcc.target/powerpc/ppc-fpconv-4.c | 9 +- .../gcc.target/powerpc/ppc-fpconv-5.c | 14 +- .../gcc.target/powerpc/ppc-fpconv-6.c | 9 +- .../gcc.target/powerpc/ppc-fpconv-7.c | 9 +- .../gcc.target/powerpc/ppc-fpconv-8.c | 9 +- .../gcc.target/powerpc/ppc-fpconv-9.c | 3 +- gcc/testsuite/gcc.target/powerpc/ppc-round.c | 8 +- 17 files changed, 270 insertions(+), 172 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 70a7c0587c7..f7587e1c388 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,62 @@ +2014-11-14 Michael Meissner + + * config/rs6000/predicates.md (easy_fp_constant): Delete redunant + tests for 0.0. + + * config/rs6000/vector.md (VEC_R): Move secondary reload support + insns to rs6000.md from vector.md. + (reload___store): Likewise. + (reload___load): Likewise. + (vec_reload_and_plus_): Likewise. + + * config/rs6000/rs6000.md (Fa): New mode attribute to give + constraint for the Altivec registers for a type. + (RELOAD): New mode iterator for all of the types that have + secondary reload address support to load up a base register. + (extendsfdf2_fpr): Use correct constraint. + (copysign3_fcpsgn): For SFmode, use correct xscpsgndp + instruction. + (floatsi2_lfiwax): Add support for -mupper-regs-{sf,df}. + Generate the non-VSX instruction if all registers were FPRs. Do + not use the patterns in vsx.md for scalar operations. + (floatsi2_lfiwax_mem): Likewise. + (floatunssi2_lfiwzx): Likewise. + (floatunssi2_lfiwzx_mem): Likewise. + (fix_truncdi2_fctidz): Likewise. + (fixuns_truncdi2_fctiduz): Likewise. + (fctiwz_): Likewise. + (fctiwuz_): Likewise. + (friz): Likewise. + (floatdidf2_fpr): Likewise. + (floatdidf2_mem): Likewise. + (floatunsdidf2): Likewise. + (floatunsdidf2_fcfidu): Likewise. + (floatunsdidf2_mem): Likewise. + (floatdisf2_fcfids): Likewise. + (floatdisf2_mem): Likewise. + (floatdisf2_internal1): Add explicit test for not FCFIDS to make + it more obvious that the code is for pre-ISA 2.06 machines. + (floatdisf2_internal2): Likewise. + (floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}. + Generate the non-VSX instruction if all registers were FPRs. Do + not use the patterns in vsx.md for scalar operations. + (floatunsdisf2_mem): Likewise. + (reload___store): Move the reload + handlers here from vector.md, and expand the types we generate + reload handlers for. + (reload___load): Likewise. + (vec_reload_and_plus_): Likewise. + + * config/rs6000/vsx.md (vsx_float2): Only provide the + vector forms of the instructions. Move VSX scalar forms to + rs6000.md, and add support for -mupper-regs-sf. + (vsx_floatuns2): Likewise. + (vsx_fix_trunc2): Likewise. + (vsx_fixuns_trunc2): Likewise. + (vsx_float_fix_2): Delete DF version, rename to + vsx_float_fix_v2df2. + (vsx_float_fix_v2df2): Likewise. + 2014-11-14 Martin Jambor * ipa-prop.h (jump_func_type): Removed value IPA_JF_KNOWN_TYPE. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index ae6e3ed6064..8abac7ee128 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -479,10 +479,6 @@ && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); case DFmode: - /* The constant 0.f is easy under VSX. */ - if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode)) - return 1; - /* Force constants to memory before reload to utilize compress_float_constant. Avoid this when flag_unsafe_math_optimizations is enabled @@ -500,10 +496,6 @@ && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); case SFmode: - /* The constant 0.f is easy. */ - if (op == CONST0_RTX (SFmode)) - return 1; - /* Force constants to memory before reload to utilize compress_float_constant. Avoid this when flag_unsafe_math_optimizations is enabled diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8ce53a5069c..4d58707fa26 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -442,6 +442,9 @@ ; SF/DF constraint for arithmetic on VSX registers (define_mode_attr Fv [(SF "wy") (DF "ws")]) +; SF/DF constraint for arithmetic on altivec registers +(define_mode_attr Fa [(SF "wu") (DF "wv")]) + ; s/d suffix for things like fp_addsub_s/fp_addsub_d (define_mode_attr Fs [(SF "s") (DF "d")]) @@ -589,6 +592,12 @@ (V2DI "wa,v,r,0,0") (V2DF "wa,v,r,0,0") (V1TI "wa,v,r,0,0")]) + +;; Reload iterator for creating the function to allocate a base register to +;; supplement addressing modes. +(define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI + SF SD SI DF DD DI TI PTI]) + ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -4952,7 +4961,7 @@ "") (define_insn_and_split "*extendsfdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv") + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu") (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "@ @@ -5057,7 +5066,7 @@ "TARGET__FPR && TARGET_CMPB" "@ fcpsgn %0,%2,%1 - xscpsgn %x0,%x2,%x1" + xscpsgndp %x0,%x2,%x1" [(set_attr "type" "fp")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a @@ -5329,9 +5338,9 @@ ; not be needed and also in case the insns are deleted as dead code. (define_insn_and_split "floatsi2_lfiwax" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=d"))] + (clobber (match_scratch:DI 2 "=wj"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX && && can_create_pseudo_p ()" "#" @@ -5370,7 +5379,7 @@ (set_attr "type" "fpload")]) (define_insn_and_split "floatsi2_lfiwax_mem" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") (float:SFDF (sign_extend:DI (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z")))) @@ -5404,9 +5413,9 @@ [(set_attr "type" "fpload,fpload,mftgpr")]) (define_insn_and_split "floatunssi2_lfiwzx" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=d"))] + (clobber (match_scratch:DI 2 "=wj"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && " "#" @@ -5445,7 +5454,7 @@ (set_attr "type" "fpload")]) (define_insn_and_split "floatunssi2_lfiwzx_mem" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") (unsigned_float:SFDF (zero_extend:DI (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z")))) @@ -5758,11 +5767,13 @@ "") (define_insn "*fix_truncdi2_fctidz" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS - && TARGET_FCFID && !VECTOR_UNIT_VSX_P (mode)" - "fctidz %0,%1" + && TARGET_FCFID" + "@ + fctidz %0,%1 + xscvdpsxds %x0,%x1" [(set_attr "type" "fp")]) (define_expand "fixuns_truncsi2" @@ -5828,11 +5839,13 @@ "") (define_insn "*fixuns_truncdi2_fctiduz" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS - && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (mode)" - "fctiduz %0,%1" + && TARGET_FCTIDUZ" + "@ + fctiduz %0,%1 + xscvdpuxds %x0,%x1" [(set_attr "type" "fp")]) ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) @@ -5840,32 +5853,37 @@ ; because the first makes it clear that operand 0 is not live ; before the instruction. (define_insn "fctiwz_" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWZ))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" - "fctiwz %0,%1" + "@ + fctiwz %0,%1 + xscvdpsxws %x0,%x1" [(set_attr "type" "fp")]) (define_insn "fctiwuz_" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") (unspec:DI [(unsigned_fix:SI - (match_operand:SFDF 1 "gpc_reg_operand" ""))] + (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWUZ))] "TARGET_HARD_FLOAT && TARGET_FPRS && && TARGET_FCTIWUZ" - "fctiwuz %0,%1" + "@ + fctiwuz %0,%1 + xscvdpuxws %x0,%x1" [(set_attr "type" "fp")]) ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since ;; since the friz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. (define_insn "*friz" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") + (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND - && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations - && !flag_trapping_math && TARGET_FRIZ" - "friz %0,%1" + && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" + "@ + friz %0,%1 + xsrdpiz %x0,%x1" [(set_attr "type" "fp")]) ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a @@ -6048,11 +6066,12 @@ "") (define_insn "*floatdidf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS - && !VECTOR_UNIT_VSX_P (DFmode)" - "fcfid %0,%1" + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") + (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" + "@ + fcfid %0,%1 + xscvsxddp %x0,%x1" [(set_attr "type" "fp")]) ; Allow the combiner to merge source memory operands to the conversion so that @@ -6061,9 +6080,9 @@ ; hit. We will split after reload to avoid the trip through the GPRs (define_insn_and_split "*floatdidf2_mem" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (float:DF (match_operand:DI 1 "memory_operand" "m"))) - (clobber (match_scratch:DI 2 "=d"))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") + (float:DF (match_operand:DI 1 "memory_operand" "m,Z"))) + (clobber (match_scratch:DI 2 "=d,wi"))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID" "#" "&& reload_completed" @@ -6077,21 +6096,23 @@ [(set (match_operand:DF 0 "gpc_reg_operand" "") (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))" + "TARGET_HARD_FLOAT && TARGET_FCFIDU" "") (define_insn "*floatunsdidf2_fcfidu" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)" - "fcfidu %0,%1" + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") + (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + "TARGET_HARD_FLOAT && TARGET_FCFIDU" + "@ + fcfidu %0,%1 + xscvuxddp %x0,%x1" [(set_attr "type" "fp") (set_attr "length" "4")]) (define_insn_and_split "*floatunsdidf2_mem" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m"))) - (clobber (match_scratch:DI 2 "=d"))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") + (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z"))) + (clobber (match_scratch:DI 2 "=d,wi"))] "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))" "#" "&& reload_completed" @@ -6124,17 +6145,19 @@ }") (define_insn "floatdisf2_fcfids" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy") + (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS" - "fcfids %0,%1" + "@ + fcfids %0,%1 + xscvsxdsp %x0,%x1" [(set_attr "type" "fp")]) (define_insn_and_split "*floatdisf2_mem" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (float:SF (match_operand:DI 1 "memory_operand" "m"))) - (clobber (match_scratch:DI 2 "=f"))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy") + (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z"))) + (clobber (match_scratch:DI 2 "=d,d,wi"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS" "#" @@ -6156,7 +6179,8 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (float:SF (match_operand:DI 1 "gpc_reg_operand" "d"))) (clobber (match_scratch:DF 2 "=d"))] - "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT + && !TARGET_FCFIDS" "#" "&& reload_completed" [(set (match_dup 2) @@ -6191,7 +6215,8 @@ (label_ref (match_operand:DI 2 "" "")) (pc))) (set (match_dup 0) (match_dup 1))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT + && !TARGET_FCFIDS" " { operands[3] = gen_reg_rtx (DImode); @@ -6206,17 +6231,19 @@ "") (define_insn "floatunsdisf2_fcfidus" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu") + (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" - "fcfidus %0,%1" + "@ + fcfidus %0,%1 + xscvuxdsp %x0,%x1" [(set_attr "type" "fp")]) (define_insn_and_split "*floatunsdisf2_mem" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m"))) - (clobber (match_scratch:DI 2 "=f"))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy") + (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z"))) + (clobber (match_scratch:DI 2 "=d,d,wi"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" "#" @@ -8414,6 +8441,50 @@ DONE; }) + +;; Reload patterns for various types using the vector registers. We may need +;; an additional base register to convert the reg+offset addressing to reg+reg +;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an +;; index register for gpr registers. +(define_expand "reload___store" + [(parallel [(match_operand:RELOAD 0 "memory_operand" "m") + (match_operand:RELOAD 1 "gpc_reg_operand" "wa") + (match_operand:P 2 "register_operand" "=b")])] + "" +{ + rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true); + DONE; +}) + +(define_expand "reload___load" + [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa") + (match_operand:RELOAD 1 "memory_operand" "m") + (match_operand:P 2 "register_operand" "=b")])] + "" +{ + rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false); + DONE; +}) + + +;; Reload sometimes tries to move the address to a GPR, and can generate +;; invalid RTL for addresses involving AND -16. Allow addresses involving +;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16. + +(define_insn_and_split "*vec_reload_and_plus_" + [(set (match_operand:P 0 "gpc_reg_operand" "=b") + (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_cint_operand" "rI")) + (const_int -16)))] + "TARGET_ALTIVEC && (reload_in_progress || reload_completed)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (plus:P (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (and:P (match_dup 0) + (const_int -16)))]) ;; Power8 merge instructions to allow direct move to/from floating point ;; registers in 32-bit mode. We use TF mode to get two registers to move the diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 04f453877da..e2946bd6e31 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -53,10 +53,6 @@ ;; Vector modes for 64-bit base types (define_mode_iterator VEC_64 [V2DI V2DF]) -;; Vector reload iterator -(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI - SF SD SI DF DD DI TI]) - ;; Base type from vector mode (define_mode_attr VEC_base [(V16QI "QI") (V8HI "HI") @@ -184,49 +180,6 @@ }") - -;; Reload patterns for vector operations. We may need an additional base -;; register to convert the reg+offset addressing to reg+reg for vector -;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index -;; register for gpr registers. -(define_expand "reload___store" - [(parallel [(match_operand:VEC_R 0 "memory_operand" "m") - (match_operand:VEC_R 1 "gpc_reg_operand" "r") - (match_operand:P 2 "register_operand" "=&b")])] - "" -{ - rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true); - DONE; -}) - -(define_expand "reload___load" - [(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r") - (match_operand:VEC_R 1 "memory_operand" "m") - (match_operand:P 2 "register_operand" "=&b")])] - "" -{ - rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false); - DONE; -}) - -;; Reload sometimes tries to move the address to a GPR, and can generate -;; invalid RTL for addresses involving AND -16. Allow addresses involving -;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16. - -(define_insn_and_split "*vec_reload_and_plus_" - [(set (match_operand:P 0 "gpc_reg_operand" "=b") - (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r") - (match_operand:P 2 "reg_or_cint_operand" "rI")) - (const_int -16)))] - "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (plus:P (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (and:P (match_dup 0) - (const_int -16)))]) ;; Generic floating point vector arithmetic support (define_expand "add3" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7aa0f12d8e0..27d464e07f7 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1198,24 +1198,24 @@ ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. ;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. (define_insn "vsx_float2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?") - (float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] + [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=,?") + (float:VSX_F (match_operand: 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" - "xcvsx %x0,%x1" + "xvcvsx %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_floatuns2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?") - (unsigned_float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] + [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=,?") + (unsigned_float:VSX_F (match_operand: 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" - "xcvux %x0,%x1" + "xvcvux %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_fix_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=,?") - (fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",")))] + (fix: (match_operand:VSX_F 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvsxs %x0,%x1" [(set_attr "type" "") @@ -1223,7 +1223,7 @@ (define_insn "vsx_fixuns_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=,?") - (unsigned_fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",")))] + (unsigned_fix: (match_operand:VSX_F 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvuxs %x0,%x1" [(set_attr "type" "") @@ -1526,19 +1526,19 @@ [(set_attr "type" "vecdouble")]) ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since -;; since the xsrdpiz instruction does not truncate the value if the floating +;; since the xvrdpiz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. -(define_insn "*vsx_float_fix_2" - [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=,?") - (float:VSX_DF - (fix: - (match_operand:VSX_DF 1 "vsx_register_operand" ",?"))))] +(define_insn "*vsx_float_fix_v2df2" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,?wa") + (float:V2DF + (fix:V2DI + (match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_VSX_P (mode) && flag_unsafe_math_optimizations + && VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" - "xriz %x0,%x1" - [(set_attr "type" "") - (set_attr "fp_type" "")]) + "xvrdpiz %x0,%x1" + [(set_attr "type" "vecdouble") + (set_attr "fp_type" "fp_addsub_d")]) ;; Permute operations diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 46493f225e3..2829167e950 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2014-11-14 Michael Meissner + + * gcc.target/powerpc/ppc-fpconv-1.c: Adjust for -mupper-regs-df + changes. + * gcc.target/powerpc/ppc-fpconv-2.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-3.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-4.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-5.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-6.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-7.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-8.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-9.c: Likewise. + * gcc.target/powerpc/ppc-fpconv-10.c: Likewise. + * gcc.target/powerpc/ppc-round.c: Likewise. + 2014-11-14 Martin Jambor * g++.dg/ipa/devirt-11.C: Dont't run ipa-cp, remove times constraint diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c index cd858097130..ea20f60e1a9 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c @@ -2,13 +2,15 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ /* { dg-final { scan-assembler-times "lfiwax" 2 } } */ /* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fcfids" 3 } } */ -/* { dg-final { scan-assembler-times "fcfidus" 1 } } */ -/* { dg-final { scan-assembler-times "xscvsxddp" 3 } } */ -/* { dg-final { scan-assembler-times "xscvuxddp" 1 } } */ +/* { dg-final { scan-assembler-times "fcfids " 3 } } */ +/* { dg-final { scan-assembler-times "fcfidus " 1 } } */ +/* { dg-final { scan-assembler-times "fcfid " 3 } } */ +/* { dg-final { scan-assembler-times "fcfidu " 1 } } */ +/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ +/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ void int_to_float (float *dest, int *src) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c index c7534d4897e..11628c91840 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c @@ -2,9 +2,8 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ -/* { dg-final { scan-assembler "xsrdpiz" } } */ -/* { dg-final { scan-assembler-not "friz" } } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ +/* { dg-final { scan-assembler "friz" } } */ double round_double_llong (double a) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c index 1f8835cc066..572dec628d6 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c @@ -6,8 +6,9 @@ /* { dg-final { scan-assembler-times "lfiwax" 2 } } */ /* { dg-final { scan-assembler-not "lfiwzx" } } */ /* { dg-final { scan-assembler-times "fcfid " 10 } } */ -/* { dg-final { scan-assembler-not "fcfids" } } */ -/* { dg-final { scan-assembler-not "fcfidus" } } */ +/* { dg-final { scan-assembler-not "fcfids " } } */ +/* { dg-final { scan-assembler-not "fcfidus " } } */ +/* { dg-final { scan-assembler-not "fcfidu " } } */ /* { dg-final { scan-assembler-not "xscvsxddp" } } */ /* { dg-final { scan-assembler-not "xscvuxddp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c index 8ea0bac7132..984d3f3f07c 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c @@ -7,10 +7,11 @@ /* { dg-final { scan-assembler-not "lfiwax" } } */ /* { dg-final { scan-assembler-not "lfiwzx" } } */ /* { dg-final { scan-assembler-times "fcfid " 10 } } */ -/* { dg-final { scan-assembler-not "fcfids" } } */ -/* { dg-final { scan-assembler-not "fcfidus" } } */ -/* { dg-final { scan-assembler-not "xscvsxddp" } } */ -/* { dg-final { scan-assembler-not "xscvuxddp" } } */ +/* { dg-final { scan-assembler-not "fcfids " } } */ +/* { dg-final { scan-assembler-not "fcfidus " } } */ +/* { dg-final { scan-assembler-not "fcfidu " } } */ +/* { dg-final { scan-assembler-not "xscvsxddp " } } */ +/* { dg-final { scan-assembler-not "xscvuxddp " } } */ void int_to_float (float *dest, int *src) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c index 834f337da97..dc1f710321a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c @@ -6,10 +6,11 @@ /* { dg-final { scan-assembler-not "lfiwax" } } */ /* { dg-final { scan-assembler-not "lfiwzx" } } */ /* { dg-final { scan-assembler-not "fcfid " } } */ -/* { dg-final { scan-assembler-not "fcfids" } } */ -/* { dg-final { scan-assembler-not "fcfidus" } } */ -/* { dg-final { scan-assembler-not "xscvsxddp" } } */ -/* { dg-final { scan-assembler-not "xscvuxddp" } } */ +/* { dg-final { scan-assembler-not "fcfids " } } */ +/* { dg-final { scan-assembler-not "fcfidus " } } */ +/* { dg-final { scan-assembler-not "fcfidu " } } */ +/* { dg-final { scan-assembler-not "xscvsxddp " } } */ +/* { dg-final { scan-assembler-not "xscvuxddp " } } */ void int_to_float (float *dest, int *src) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c index 588840c35b4..c44eb08231c 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c @@ -2,13 +2,13 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ -/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz" 2 } } */ -/* { dg-final { scan-assembler-times "fctidz" 1 } } */ -/* { dg-final { scan-assembler-times "fctiduz" 1 } } */ -/* { dg-final { scan-assembler-times "xscvdpsxds" 1 } } */ -/* { dg-final { scan-assembler-times "xscvdpuxds" 1 } } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ +/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ +/* { dg-final { scan-assembler-times "fctidz " 2 } } */ +/* { dg-final { scan-assembler-times "fctiduz " 2 } } */ +/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ +/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ void float_to_int (int *dest, float src) { *dest = (int) src; } void double_to_int (int *dest, double src) { *dest = (int) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c index cd2755179c1..5282a5a4293 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c @@ -3,10 +3,11 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O3 -mcpu=power6 -ffast-math" } */ -/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ -/* { dg-final { scan-assembler-not "fctiwuz" } } */ -/* { dg-final { scan-assembler-times "fctidz" 8 } } */ -/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-not "fctiwuz " } } */ +/* { dg-final { scan-assembler-times "fctidz " 8 } } */ +/* { dg-final { scan-assembler-not "fctiduz " } } */ +/* { dg-final { scan-assembler-not "fctidu " } } */ /* { dg-final { scan-assembler-not "xscvdpsxds" } } */ /* { dg-final { scan-assembler-not "xscvdpuxds" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c index a440196c197..fa0b50edb30 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c @@ -4,10 +4,11 @@ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O3 -mcpu=power5 -ffast-math" } */ -/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ -/* { dg-final { scan-assembler-not "fctiwuz" } } */ -/* { dg-final { scan-assembler-times "fctidz" 8 } } */ -/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-not "fctiwuz " } } */ +/* { dg-final { scan-assembler-times "fctidz " 8 } } */ +/* { dg-final { scan-assembler-not "fctiduz " } } */ +/* { dg-final { scan-assembler-not "fctidu " } } */ /* { dg-final { scan-assembler-not "xscvdpsxds" } } */ /* { dg-final { scan-assembler-not "xscvdpuxds" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c index fc072a4acdc..5f1bb23c50e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c @@ -4,10 +4,11 @@ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=750" } } */ /* { dg-options "-O3 -mcpu=750 -ffast-math" } */ -/* { dg-final { scan-assembler-times "fctiwz" 6 } } */ -/* { dg-final { scan-assembler-not "fctiwuz" } } */ -/* { dg-final { scan-assembler-not "fctidz" } } */ -/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-times "fctiwz " 6 } } */ +/* { dg-final { scan-assembler-not "fctiwuz " } } */ +/* { dg-final { scan-assembler-not "fctidz " } } */ +/* { dg-final { scan-assembler-not "fctiduz " } } */ +/* { dg-final { scan-assembler-not "fctidu " } } */ /* { dg-final { scan-assembler-not "xscvdpsxds" } } */ /* { dg-final { scan-assembler-not "xscvdpuxds" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c index 3efdcaaaa94..62ead0a9e4f 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c @@ -2,7 +2,8 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ +/* { dg-final { scan-assembler-times "fctidz" 2 } } */ /* { dg-final { scan-assembler-not "lwz" } } */ /* { dg-final { scan-assembler-not "stw" } } */ /* { dg-final { scan-assembler-not "ld " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c index f1f5c3b78e7..4fc1679622d 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -2,13 +2,13 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */ /* { dg-final { scan-assembler-times "stfiwx" 4 } } */ /* { dg-final { scan-assembler-times "lfiwax" 2 } } */ /* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ -/* { dg-final { scan-assembler-times "xscvsxddp" 2 } } */ -/* { dg-final { scan-assembler-times "fcfids" 2 } } */ +/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ +/* { dg-final { scan-assembler-times "fcfids " 2 } } */ /* { dg-final { scan-assembler-not "lwz" } } */ /* { dg-final { scan-assembler-not "stw" } } */ -- 2.30.2