From 0c3f8f703df41927fd7124215fc8d13eb5268e08 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 8 Apr 2014 15:25:49 +0200 Subject: [PATCH] targets/simple: add dummy SDRAM + flash boot address --- targets/simple.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/targets/simple.py b/targets/simple.py index ed8fbdee..4e5f7521 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -1,4 +1,5 @@ from migen.fhdl.std import * +from migen.bus import wishbone from misoclib import gpio, spiflash from misoclib.gensoc import GenSoC @@ -19,8 +20,15 @@ class SimpleSoC(GenSoC): # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) + self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) + # TODO: use on-board SDRAM instead of block RAM + sys_ram_size = 32*1024 + self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) + self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) + self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size) + self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) default_subtarget = SimpleSoC -- 2.30.2