From 0c4e20c35ea063be5ad9464b1b9e3c35b5c7a30a Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 13 Dec 2021 11:41:24 +0100 Subject: [PATCH] add signals to port interface as descibed in bug 756 --- src/soc/config/test/test_pi2ls.py | 4 ++-- src/soc/experiment/pimem.py | 14 +++++++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index 4949bd05..b2a32965 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -53,7 +53,7 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0): yield port1.is_dcbz_i.eq(is_dcbz) # reset dcbz too yield port1.is_st_i.eq(1) # indicate ST yield port1.data_len.eq(datalen) # ST length (1/2/4/8) - yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real) + yield port1.priv_mode.eq(~msr_pr) # MSR PR bit (1==>virt, 0==>real) yield port1.addr.data.eq(addr) # set address yield port1.addr.ok.eq(1) # set ok @@ -139,7 +139,7 @@ def pi_ld(port1, addr, datalen, msr_pr=0): # set up a LD on the port. address first: yield port1.is_ld_i.eq(1) # indicate LD yield port1.data_len.eq(datalen) # LD length (1/2/4/8) - yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real) + yield port1.priv_mode.eq(~msr_pr) # MSR PR bit (1==>virt, 0==>real) yield port1.addr.data.eq(addr) # set address yield port1.addr.ok.eq(1) # set ok diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 44eaeebe..c1bd168c 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -117,7 +117,13 @@ class PortInterface(RecordObject): # additional "modes" self.is_nc = Signal() # no cacheing - self.msr_pr = Signal() # 1==virtual, 0==privileged + + #only priv_mode = not msr_pr is used currently + # TODO: connect signals + self.virt_mode = Signal() # ctrl.msr(MSR_DR); + self.priv_mode = Signal() # not ctrl.msr(MSR_PR); + self.mode_32bit = Signal() # not ctrl.msr(MSR_SF); + self.is_dcbz_i = Signal(reset_less=True) # mmu @@ -139,7 +145,9 @@ class PortInterface(RecordObject): self.addr.data.eq(inport.addr.data), self.addr.ok.eq(inport.addr.ok), self.st.eq(inport.st), - self.msr_pr.eq(inport.msr_pr), + self.virt_mode.eq(inport.virt_mode), + self.priv_mode.eq(inport.priv_mode), + self.mode_32bit.eq(inport.mode_32bit), inport.ld.eq(self.ld), inport.busy_o.eq(self.busy_o), inport.addr_ok_o.eq(self.addr_ok_o), @@ -212,7 +220,7 @@ class PortInterfaceBase(Elaboratable): pi = self.pi comb += lds.eq(pi.is_ld_i) # ld-req signals comb += sts.eq(pi.is_st_i) # st-req signals - pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv + pr = ~pi.priv_mode # detect busy "edge" busy_delay = Signal() -- 2.30.2