From 0c63205bf1e7b139004f3859e85a889c52fc4a71 Mon Sep 17 00:00:00 2001
From: programmerjake <programmerjake@web>
Date: Thu, 23 Apr 2020 06:43:23 +0100
Subject: [PATCH] add link to alternative memory interface idea

---
 3d_gpu/architecture/memory_and_cache.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index 85f84dac3..ac02a3248 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -38,6 +38,10 @@ Basic diagram:
 * Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
   and it is Wishbone compliant.
 
+## Alternative Design Idea
+
+[[alternative-design-idea]]
+
 # 28-45nm Quad-Core SoC
 
 This is full SMP, requires analog PLLs, clock gating, full SMP
-- 
2.30.2