From 0c63a8ee9168d4d3cb0e7b97b78e324f65e1a22a Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Wed, 13 Feb 2019 14:04:41 +0000 Subject: [PATCH] AArch64: Allow any offset for SVE addressing modes before reload. On AArch64 aarch64_classify_address has a case for when it's non-strict that will allow it to accept any byte offset from a reg when validating an address in a given addressing mode. This because reload would later make the address valid. SVE however requires the address always be valid, but currently allows any address when a MEM + offset is used. This causes an ICE as nothing later forces the address to be legitimate. The patch forces aarch64_emit_sve_pred_move via expand_insn to ensure that the addressing mode is valid for any loads/stores it creates, which follows the SVE way of handling address classifications. gcc/ChangeLog: PR target/88847 * config/aarch64/aarch64-sve.md (*pred_mov, pred_mov): Expose as @aarch64_pred_mov. * config/aarch64/aarch64.c (aarch64_classify_address): Use expand_insn which legitimizes operands. gcc/testsuite/ChangeLog: PR target/88847 * gcc.target/aarch64/sve/pr88847.c: New test. From-SVN: r268845 --- gcc/ChangeLog | 8 +++++++ gcc/config/aarch64/aarch64-sve.md | 4 ++-- gcc/config/aarch64/aarch64.c | 9 +++++--- gcc/testsuite/ChangeLog | 5 +++++ .../gcc.target/aarch64/sve/pr88847.c | 21 +++++++++++++++++++ 5 files changed, 42 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr88847.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a6ef20cb716..76cef68bed1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-02-13 Tamar Christina + + PR target/88847 + * config/aarch64/aarch64-sve.md (*pred_mov, pred_mov): + Expose as @aarch64_pred_mov. + * config/aarch64/aarch64.c (aarch64_classify_address): + Use expand_insn which legitimizes operands. + 2019-02-13 Martin Liska * builtins.h (expand_builtin_with_bounds): Remove declaration. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 703708b6788..3f39c4c5b63 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -170,7 +170,7 @@ ;; all-true. Note that this pattern is generated directly by ;; aarch64_emit_sve_pred_move, so changes to this pattern will ;; need changes there as well. -(define_insn_and_split "*pred_mov" +(define_insn_and_split "@aarch64_pred_mov" [(set (match_operand:SVE_ALL 0 "nonimmediate_operand" "=w, w, m") (unspec:SVE_ALL [(match_operand: 1 "register_operand" "Upl, Upl, Upl") @@ -404,7 +404,7 @@ ;; Predicated structure moves. This works for both endiannesses but in ;; practice is only useful for big-endian. -(define_insn_and_split "pred_mov" +(define_insn_and_split "@aarch64_pred_mov" [(set (match_operand:SVE_STRUCT 0 "aarch64_sve_struct_nonimmediate_operand" "=w, w, Utx") (unspec:SVE_STRUCT [(match_operand: 1 "register_operand" "Upl, Upl, Upl") diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d7c453cdad0..1fa28fe82fe 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3414,9 +3414,12 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm, void aarch64_emit_sve_pred_move (rtx dest, rtx pred, rtx src) { - emit_insn (gen_rtx_SET (dest, gen_rtx_UNSPEC (GET_MODE (dest), - gen_rtvec (2, pred, src), - UNSPEC_MERGE_PTRUE))); + expand_operand ops[3]; + machine_mode mode = GET_MODE (dest); + create_output_operand (&ops[0], dest, mode); + create_input_operand (&ops[1], pred, GET_MODE(pred)); + create_input_operand (&ops[2], src, mode); + expand_insn (code_for_aarch64_pred_mov (mode), 3, ops); } /* Expand a pre-RA SVE data move from SRC to DEST in which at least one diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d3223f0e313..5f220ccae10 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-02-13 Tamar Christina + + PR target/88847 + * gcc.target/aarch64/sve/pr88847.c: New test. + 2019-02-13 Jonathan Wakely Jakub Jelinek diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c b/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c new file mode 100644 index 00000000000..b7504add9a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c @@ -0,0 +1,21 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-additional-options "-O0 -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef struct _b { + __attribute__((__vector_size__(32))) int a[2]; +} b; + +b *c; + +void +foo (void) +{ + char *p = '\0'; + b e = c[0]; +} + +/* { dg-final { scan-assembler {\tld1w\tz[0-9]+.s, p[0-9]+/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz[0-9]+.s, p[0-9]+/z, \[x[0-9]+, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz[0-9]+.s, p[0-9]+, \[(sp|x[0-9]+)\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz[0-9]+.s, p[0-9]+, \[(sp|x[0-9]+), #1, mul vl\]\n} } } */ + -- 2.30.2