From 0c67393313f125b6fca70614f10c2ec61116dd82 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 01:56:16 +0200 Subject: [PATCH] Added support for $bu0 to verilog backend --- backends/verilog/verilog_backend.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d7fe4c4e2..6be26329a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -581,6 +581,22 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$bu0") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->connections["\\Y"]); + if (cell->parameters["\\A_SIGNED"].as_bool()) { + fprintf(f, " = $signed("); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, ");\n"); + } else { + fprintf(f, " = { 1'b0, "); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, " };\n"); + } + return true; + } + if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); -- 2.30.2