From 0c842b7ff840db1cfa32b7f3ed8f58abdd2d5976 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 18:08:56 +0100 Subject: [PATCH] new fast3 needs to be remapped to fast1 port in "reduced ports" case in core --- src/soc/simple/core.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index b5fbbebe..18d62eba 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -365,6 +365,8 @@ class NonProductionCore(Elaboratable): fuspecs['fast1'] = [fuspecs.pop('fast1')] if 'fast2' in fuspecs: fuspecs['fast1'].append(fuspecs.pop('fast2')) + if 'fast3' in fuspecs: + fuspecs['fast1'].append(fuspecs.pop('fast3')) # for each named regfile port, connect up all FUs to that port for (regname, fspec) in sort_fuspecs(fuspecs): @@ -491,6 +493,8 @@ class NonProductionCore(Elaboratable): fuspecs['fast1'] = [fuspecs.pop('fast1')] if 'fast2' in fuspecs: fuspecs['fast1'].append(fuspecs.pop('fast2')) + if 'fast3' in fuspecs: + fuspecs['fast1'].append(fuspecs.pop('fast3')) for (regname, fspec) in sort_fuspecs(fuspecs): self.connect_wrport(m, fu_bitdict, wrpickers, -- 2.30.2