From 0cad80e935afeb3c5a9b71024a5ced4d8a8f3c97 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 May 2019 10:59:03 +0200 Subject: [PATCH] cpu/vexriscv: update submodule (new linux variant) --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 66faa6ec..c6dfccaa 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 66faa6ece6551abac424146f9a27960ba10f4cf8 +Subproject commit c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0 -- 2.30.2