From 0cbe70eaa40056a9d41070652282694cd7285b1a Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Fri, 22 Apr 2016 19:08:19 -0700 Subject: [PATCH] Fixed typo --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 40d79aeae..706e955b6 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge RSTN) begin + always @(posedge clk, negedge nRST) begin if(!nRST) shreg = 0; -- 2.30.2