From 0ccc086209ff8236bb5f0a6e7b3eb44b231a5026 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 26 Sep 2023 16:08:42 +0100 Subject: [PATCH] add english language description for lbzupx --- openpower/isa/pifixedload.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn index 045d3262..73b72db3 100644 --- a/openpower/isa/pifixedload.mdwn +++ b/openpower/isa/pifixedload.mdwn @@ -46,6 +46,16 @@ Pseudo-code: RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- (RA) + (RB) +Description: + + Let the effective address (EA) be register RA. + The byte in storage addressed by EA is loaded into + RT[56:63]. RT[0:55] are set to 0. + + The sum (RA) + (RB) is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2