From 0ccc7229c02449618209a20d66b9fa07e3ea79f2 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 30 Mar 2021 09:38:00 -0400
Subject: [PATCH] preproc: test coverage for #2712

---
 tests/verilog/ifdef_nest.ys         | 7 +++++++
 tests/verilog/ifdef_unterminated.ys | 4 ++++
 tests/verilog/unmatched_endif_2.ys  | 7 +++++++
 3 files changed, 18 insertions(+)
 create mode 100644 tests/verilog/ifdef_nest.ys
 create mode 100644 tests/verilog/ifdef_unterminated.ys
 create mode 100644 tests/verilog/unmatched_endif_2.ys

diff --git a/tests/verilog/ifdef_nest.ys b/tests/verilog/ifdef_nest.ys
new file mode 100644
index 000000000..2202109aa
--- /dev/null
+++ b/tests/verilog/ifdef_nest.ys
@@ -0,0 +1,7 @@
+read_verilog <<EOF
+`ifndef a
+`ifdef b
+`endif
+`else
+`endif
+EOF
diff --git a/tests/verilog/ifdef_unterminated.ys b/tests/verilog/ifdef_unterminated.ys
new file mode 100644
index 000000000..ce511fa8f
--- /dev/null
+++ b/tests/verilog/ifdef_unterminated.ys
@@ -0,0 +1,4 @@
+logger -expect error "Unterminated preprocessor conditional!" 1
+read_verilog <<EOF
+`ifndef a
+EOF
diff --git a/tests/verilog/unmatched_endif_2.ys b/tests/verilog/unmatched_endif_2.ys
new file mode 100644
index 000000000..2ee084170
--- /dev/null
+++ b/tests/verilog/unmatched_endif_2.ys
@@ -0,0 +1,7 @@
+logger -expect error "Found `endif outside of macro conditional branch!" 1
+read_verilog <<EOF
+`ifndef a
+`else
+`endif
+`endif
+EOF
-- 
2.30.2