From 0cd7953ece40a9d2ce57b220adc7857ceb180932 Mon Sep 17 00:00:00 2001 From: Boyuan Zhang Date: Tue, 5 Mar 2019 17:48:52 -0500 Subject: [PATCH] radeon/vcn: add direct register bool VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers Signed-off-by: Boyuan Zhang Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeon/radeon_vcn_dec.c | 2 ++ src/gallium/drivers/radeon/radeon_vcn_dec.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c index 99293411b0d..5bc73c1897e 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c @@ -1602,11 +1602,13 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1; dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD; dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL; + dec->jpg.direct_reg = true; } else { dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0; dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1; dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD; dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL; + dec->jpg.direct_reg = false; } map_msg_fb_it_probs_buf(dec); diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h b/src/gallium/drivers/radeon/radeon_vcn_dec.h index 3ba42f3b77c..f079b94dff5 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.h +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h @@ -753,6 +753,7 @@ struct jpeg_params { unsigned dt_uv_pitch; unsigned dt_luma_top_offset; unsigned dt_chroma_top_offset; + bool direct_reg; }; struct radeon_decoder { -- 2.30.2