From 0cd8c83ff34d11b4fed0416f04ba069ccf79580d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 25 Mar 2022 14:53:01 +0000 Subject: [PATCH] increase time for power-on-delay to 2^25 in ECP5 --- src/crg.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/crg.py b/src/crg.py index af2ccb1..a5370b7 100644 --- a/src/crg.py +++ b/src/crg.py @@ -206,7 +206,7 @@ class ECPIX5CRG(Elaboratable): m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset) # Power-on delay (655us) - podcnt = Signal(23, reset=-1) + podcnt = Signal(25, reset=-1) pod_done = Signal() with m.If((podcnt != 0) & pll.locked): m.d.rawclk += podcnt.eq(podcnt-1) -- 2.30.2