From 0cf0bc67f6fad8653edb7656080f7f61394c92b4 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Mon, 18 Dec 2017 16:26:47 +0100 Subject: [PATCH] [ARC] Update (u)maddsidi patterns. The accumulator registers are freely used by the compiler. However, there are a number of instructions which are having an intrinsic use of these registers. Update patterns to inform the compiler which ones. gcc/ 2017-09-19 Claudiu Zissulescu * config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern. (umaddsidi4,umaddsidi4): Likewise. gcc/testsuite 2017-09-19 Claudiu Zissulescu * gcc.target/arc/tumaddsidi4.c: New test. From-SVN: r255779 --- gcc/ChangeLog | 5 ++++ gcc/config/arc/arc.md | 32 +++++++++++++++++++--- gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 14 ++++++++++ 4 files changed, 51 insertions(+), 4 deletions(-) create mode 100755 gcc/testsuite/gcc.target/arc/tumaddsidi4.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84046fffb17..5cd14bbaaa9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-12-18 Claudiu Zissulescu + + * config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern. + (umaddsidi4, umaddsidi_split): Likewise. + 2017-12-18 Claudiu Zissulescu * config/arc/arc.c (arc_legitimate_constant_p): Always check all diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 880327c2490..575852e4210 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6155,13 +6155,25 @@ [(set_attr "length" "0")]) ;; MAC and DMPY instructions -(define_insn_and_split "maddsidi4" +(define_expand "maddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "maddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" @@ -6243,13 +6255,25 @@ (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn_and_split "umaddsidi4" +(define_expand "umaddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "umaddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 844fc960f7d..c00a20f79d6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-12-18 Claudiu Zissulescu + + * gcc.target/arc/tumaddsidi4.c: New test. + 2017-12-18 Claudiu Zissulescu * gcc.target/arc/tls-1.c: New test. diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c new file mode 100755 index 00000000000..40d2b3325f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy" } */ + +/* Check how we generate umaddsidi4 patterns. */ +long a; +long long b; +unsigned c, d; + +void fn1(void) +{ + b = d * (long long)c + a; +} + +/* { dg-final { scan-assembler "macu 0,r" } } */ -- 2.30.2