From 0d2b1333c4b4124141f7059e74b59030326b7a3b Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 27 Jun 2021 05:24:50 +0100
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 38134e48a..7d8cddd1b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -223,6 +223,10 @@ than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
 **RC1** as if Rc=1, stores CRs *but not the result*
 
+For LD/ST Modes, see and [[sv/ldst]].  Immediate and Indexed LD/ST
+are both different, in order to support a large range of features
+normally found in Vector ISAs.
+
 # ELWIDTH Encoding
 
 Default behaviour is set to 0b00 so that zeros follow the convention of
-- 
2.30.2