From 0d2db236038b6095064332018be946bab5834461 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 25 May 2015 13:55:15 +0200 Subject: [PATCH] litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink) --- misoclib/mem/litesata/core/link/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py index a723112e..f6553a0d 100644 --- a/misoclib/mem/litesata/core/link/__init__.py +++ b/misoclib/mem/litesata/core/link/__init__.py @@ -36,7 +36,7 @@ class LiteSATALinkTX(Module): # inserter CONT and scrambled data between # CONT and next primitive - cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32))) + cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32))) self.submodules += cont # datas / primitives mux -- 2.30.2