From 0d60902fd97bba4f231f8f600434b8a69562ffff Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:04:02 +0200 Subject: [PATCH] hierarchy - proc reorder --- tests/ecp5/add_sub.ys | 1 + tests/ecp5/adffs.ys | 8 ++++---- tests/ecp5/dffs.ys | 4 ++-- tests/ecp5/latches.ys | 6 +++--- tests/ecp5/logic.ys | 1 + tests/ecp5/macc.ys | 2 +- tests/ecp5/mul.ys | 1 + tests/ecp5/mux.ys | 8 ++++---- tests/ecp5/rom.ys | 1 + 9 files changed, 18 insertions(+), 14 deletions(-) diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys index 03aec6694..ee72d732f 100644 --- a/tests/ecp5/add_sub.ys +++ b/tests/ecp5/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 658f302d0..b129419d3 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index f32998232..fc15a6910 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -2,8 +2,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchp # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index 34125fea9..4f113a130 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index f60281a54..1863ea4d2 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,6 +1,6 @@ read_verilog macc.v -proc hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 132340664..0a91f892e 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index eada276ba..8cfbd541b 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys index 8a52749a1..98645ae43 100644 --- a/tests/ecp5/rom.ys +++ b/tests/ecp5/rom.ys @@ -1,4 +1,5 @@ read_verilog rom.v +hierarchy -top top proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -- 2.30.2