From 0d685ba2900734d8af4a47ef9586d511ad754ce4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 5 Jun 2018 02:09:52 -0400 Subject: [PATCH] radeonsi: make sure LS-HS vector lanes are reasonably occupied MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel --- src/gallium/drivers/radeonsi/si_state_draw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index e7f8389caf3..d61374e95ca 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -170,6 +170,14 @@ static bool si_emit_derived_tess_state(struct si_context *sctx, */ *num_patches = MIN2(*num_patches, 40); + /* Make sure that vector lanes are reasonably occupied. It probably + * doesn't matter much because this is LS-HS, and TES is likely to + * occupy significantly more CUs. + */ + unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch; + if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48) + *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch; + if (sctx->chip_class == SI) { /* SI bug workaround, related to power management. Limit LS-HS * threadgroups to only one wave. -- 2.30.2